| /openbmc/u-boot/doc/device-tree-bindings/i2c/ |
| H A D | nvidia,tegra186-bpmp-i2c.txt | 10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
21 Single-cell integer.
23 - #size-cells:
24 Single-cell integer.
26 - nvidia,bpmp-bus-id:
27 Single-cell integer.
37 compatible = "nvidia,tegra186-bpmp-i2c";
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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| H A D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
14 single interrupt must be specified.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 15 register set. These registers exist in a single contiguous block of physical
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - reg-names
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
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| H A D | srio.txt | 5 - compatible
11 Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
15 - reg
17 Value type: <prop-encoded-array>
22 - interrupts
24 Value type: <prop_encoded-array>
30 A single IRQ that handles error conditions is specified by this
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
36 Definition: A single <phandle> value that points to the RMU.
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| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | apple,aic2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
|
| H A D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
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| H A D | apple,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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| H A D | arm,vic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
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| H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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| /openbmc/u-boot/include/dt-bindings/gpio/ |
| H A D | gpio.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Most GPIO bindings include a flags cell as part of the GPIO specifier.
6 * In most cases, the format of the flags cell uses the standard values
17 /* Bit 1 express single-endedness */
26 * Open Drain/Collector is the combination of single-ended open drain interface.
27 * Open Source/Emitter is the combination of single-ended open source interface.
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
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| /openbmc/linux/include/dt-bindings/gpio/ |
| H A D | gpio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
5 * Most GPIO bindings include a flags cell as part of the GPIO specifier.
6 * In most cases, the format of the flags cell uses the standard values
17 /* Bit 1 express single-endedness */
26 * Open Drain/Collector is the combination of single-ended open drain interface.
27 * Open Source/Emitter is the combination of single-ended open source interface.
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-detect.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _detect-controls:
13 .. _detect-control-id:
28 .. flat-table::
29 :header-rows: 0
30 :stub-columns: 0
32 * - ``V4L2_DETECT_MD_MODE_DISABLED``
33 - Disable motion detection.
34 * - ``V4L2_DETECT_MD_MODE_GLOBAL``
35 - Use a single motion detection threshold.
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | max77650.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAX77650 ultra low-power PMIC from Maxim Integrated.
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 MAX77650 is an ultra-low power PMIC providing battery charging and power
14 supply for low-power IoT and wearable applications.
16 The GPIO-controller module is represented as part of the top-level PMIC
17 node. The device exposes a single GPIO line.
19 For device-tree bindings of other sub-modules (regulator, power supply,
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | pinmux_arria10.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
16 const u32 *cell; in do_pinctr_pin() local
21 cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len); in do_pinctr_pin()
22 if (!cell || len <= 0) in do_pinctr_pin()
23 return -EFAULT; in do_pinctr_pin()
25 debug("%p %d\n", cell, len); in do_pinctr_pin()
26 for (; len > 0; len -= (2 * sizeof(u32))) { in do_pinctr_pin()
27 offset = fdt32_to_cpu(*cell++); in do_pinctr_pin()
28 value = fdt32_to_cpu(*cell++); in do_pinctr_pin()
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| /openbmc/linux/Documentation/devicetree/bindings/mips/cavium/ |
| H A D | bootbus.txt | 7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
|
| /openbmc/linux/include/uapi/linux/ |
| H A D | atmdev.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmdev.h - ATM device driver declarations and various related items */
4 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
21 bits per cell: /8/53
22 max cell rate: 353207.547 cells/sec */
23 #define ATM_25_PCR ((25600000/8-8000)/54)
24 /* 25 Mbps ATM cell rate (59111) */
28 bits per cell: /8/53
29 max cell rate: 1412830.188 cells/sec */
97 /* enable or disable single-copy */
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| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | richtek,rt9471.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Richtek RT9471 3A Single Cell Switching Battery charger
10 - Alina Yu <alina_yu@richtek.com>
11 - ChiYuan Huang <cy_huang@richtek.com>
14 RT9471 is a switch-mode single cell Li-Ion/Li-Polymer battery charger for
19 https://www.richtek.com/assets/product_file/RT9471=RT9471D/DS9471D-02.pdf
28 charge-enable-gpios:
32 wakeup-source: true
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
18 a single pincontroller.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
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| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
16 second cell is used to specify optional parameters:
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| /openbmc/linux/Documentation/devicetree/bindings/spmi/ |
| H A D | qcom,spmi-pmic-arb.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
14 controller with wrapping arbitration logic to allow for multiple on-chip
15 devices to control a single SPMI master.
21 - $ref: spmi.yaml
25 const: qcom,spmi-pmic-arb
29 - items: # V1
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|