| /openbmc/linux/arch/mips/include/asm/ |
| H A D | mips-gic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
33 /* For read-write shared registers */
37 /* For read-only local registers */
42 /* For read-write local registers */
47 /* For read-only shared per-interrupt registers */
60 /* For read-write shared per-interrupt registers */
71 /* For read-only local per-interrupt registers */
78 /* For read-write local per-interrupt registers */
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| /openbmc/qemu/docs/specs/ |
| H A D | ivshmem-spec.rst | 2 Device Specification for Inter-VM shared memory device
5 The Inter-VM shared memory device (ivshmem) is designed to share a
8 shared memory area, it is modeled by QEMU as a PCI device exposing
11 The device can use a shared memory object on the host directly, or it
14 In the latter case, the device can additionally interrupt its peers, and
27 --------
31 - BAR0 holds device registers (256 Byte MMIO)
32 - BAR1 holds MSI-X table and PBA (only ivshmem-doorbell)
33 - BAR2 maps the shared memory object
37 - If you only need the shared memory part, BAR2 suffices. This way,
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| H A D | vmw_pvscsi-spec.rst | 14 The interface is based on a memory area shared between hypervisor and VM.
17 The shared memory consists of a registers area and a rings area.
21 hypervisor to VM. Data itself is transferred via virtual scatter-gather DMA.
30 issue device interrupts, and control interrupt masking.
35 There are three rings in shared memory:
53 The following interrupt types are supported by the PVSCSI device:
57 - ``PVSCSI_INTR_CMPL_0``
58 - ``PVSCSI_INTR_CMPL_1``
62 - ``PVSCSI_INTR_MSG_0``
63 - ``PVSCSI_INTR_MSG_1``
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| /openbmc/linux/drivers/net/ipa/ |
| H A D | ipa_uc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
24 * The microcontroller can generate two interrupts to the AP. One interrupt
27 * addition, the AP can interrupt the microcontroller by writing a register.
31 * AP and the IPA microcontroller. Each side writes data to the shared area
33 * to the interrupt. Some information found in the shared area is currently
34 * unused. All remaining space in the shared area is reserved, and must not
43 * struct ipa_uc_mem_area - AP/microcontroller shared memory area
44 * @command: command code (AP->microcontroller)
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | nvidia,tegra186-hsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 The features that HSP supported are shared mailboxes, shared
29 For shared mailboxes, the first cell composed of two fields:
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | st,spear3xx-shirq.txt | 1 * SPEAr Shared IRQ layer (shirq)
3 SPEAr3xx architecture includes shared/multiplexed irqs for certain set
4 of devices. The multiplexor provides a single interrupt to parent
5 interrupt controller (VIC) on behalf of a group of devices.
13 A single node in the device tree is used to describe the shared
14 interrupt multiplexor (one node for all groups). A group in the
15 interrupt controller shares config/control registers with other groups.
16 For example, a 32-bit interrupt enable/disable config register can
17 accommodate up to 4 interrupt groups.
20 - compatible: should be, either of
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| H A D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | prcm-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
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| /openbmc/qemu/include/hw/intc/ |
| H A D | mips_gic.h | 33 #define MSK(n) ((1ULL << (n)) - 1)
45 /* Register Map for Shared Section */
49 /* Shared Global Counter */
57 /* Reset Mask - Disables Interrupt */
61 /* Set Mask (WO) - Enables Interrupt */
65 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
101 /* User-Mode Visible Section Register */
102 /* Read-only alias for GIC Shared CounterLo */
104 /* Read-only alias for GIC Shared CounterHi */
160 #define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */
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| /openbmc/linux/Documentation/devicetree/bindings/display/ti/ |
| H A D | ti,j721e-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
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| /openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,smsm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory State Machine facilitates broadcasting of single bit state
25 '#address-cells':
28 qcom,local-host:
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| H A D | qcom,smp2p.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Point 2 Point
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory Point to Point (SMP2P) protocol facilitates communication
16 of a single 32-bit value between two processors. Each value has a single
35 $ref: /schemas/types.yaml#/definitions/phandle-array
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| /openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/ |
| H A D | hw_atl2_llh.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /* Set TX Interrupt Moderation Control Register */
41 /* set tx random TC-queue mapping enable bit */
72 /* get data from firmware shared input buffer */
76 /* set data into firmware shared input buffer */
80 /* get data from firmware shared output buffer */
84 /* set host finished write shared buffer indication */
87 /* get mcp finished read shared buffer indication */
96 /* get host interrupt request */
99 /* clear host interrupt request */
|
| /openbmc/linux/Documentation/power/ |
| H A D | suspend-and-interrupts.rst | 10 -----------------------------------
12 Device interrupt request lines (IRQs) are generally disabled during system
14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all
21 interrupt handlers for shared IRQs that device drivers implementing them were
29 Device IRQs are re-enabled during system resume, right before the "early" phase
30 of resuming devices (that is, before starting to execute ->resume_early
35 ------------------------
38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
41 but also to IPIs and to some other special-purpose interrupts.
44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to
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| /openbmc/qemu/docs/system/devices/ |
| H A D | ivshmem-flat.rst | 1 Inter-VM Shared Memory Flat Device
2 ----------------------------------
4 The ivshmem-flat device is meant to be used on machines that lack a PCI bus,
6 a PCI device. Machines like those with a Cortex-M MCU are good candidates to use
7 the ivshmem-flat device. Also, since the flat version maps the control and
12 Similar to the ivshmem device, the ivshmem-flat device supports both peer
13 notification via HW interrupts and Inter-VM shared memory. This allows the
16 running Linux), and an arm VM (using the ivshmem-flat device and running Zephyr
19 The ivshmem-flat device does not support the use of a ``memdev`` option (see
21 distribute the proper shared memory file descriptor and the eventfd(s) to notify
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp15xx-osd32.dtsi | 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 #include "stm32mp15-pinctrl.dtsi"
9 #include <dt-bindings/mfd/st,stpmic1.h>
12 reserved-memory {
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "shared-dma-pool";
20 no-map;
24 compatible = "shared-dma-pool";
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| H A D | stm32mp157c-odyssey-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
17 model = "Seeed Studio Odyssey-STM32MP157C SOM";
18 compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
25 reserved-memory {
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| H A D | stm32mp15xx-dhcor-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxac-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/mfd/st,stpmic1.h>
23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "shared-dma-pool";
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | sprd,gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 The controller's registers are organized as sets of sixteen 16-bit
18 interrupt is shared for all of the banks handled by the controller.
23 - const: sprd,sc9860-gpio
24 - items:
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| /openbmc/linux/drivers/tee/optee/ |
| H A D | optee_smc.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2021, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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| /openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/ |
| H A D | southcluster.asl | 1 /* SPDX-License-Identifier: GPL-2.0+ */
72 If (LEqual(Arg0, ToUUID("33db4d5b-1ff7-401c-9657-7441c03dd766"))) {
194 * http://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt
198 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
201 "cs-gpios", Package () {
328 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
330 Package () { "host-wakeup-gpios", Package () { ^BTH0, 0, 0, 0 } },
331 Package () { "device-wakeup-gpios", Package () { ^BTH0, 1, 0, 0 } },
332 Package () { "shutdown-gpios", Package () { ^BTH0, 2, 0, 0 } },
370 * --------------------
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| /openbmc/u-boot/doc/device-tree-bindings/mailbox/ |
| H A D | nvidia,tegra186-hsp.txt | 9 The features that HSP supported are shared mailboxes, shared semaphores,
13 - name : Should be hsp
14 - compatible
17 - "nvidia,tegra186-hsp"
18 - reg : Offset and length of the register set for the device.
19 - interrupt-names
21 Contains a list of names for the interrupts described by the interrupt
23 - "doorbell"
24 Users of this binding MUST look up entries in the interrupt property
25 by name, using this interrupt-names property to do so.
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| /openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| H A D | gpio.asl | 1 /* SPDX-License-Identifier: GPL-2.0+ */
19 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
48 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
77 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
|
| /openbmc/linux/arch/arm/mach-shmobile/ |
| H A D | regulator-quirk-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 da9063(L)/da9210 regulator quirk
6 * regulators. All of these regulators have their interrupt request lines
7 * tied to the same interrupt pin (IRQ2) on the SoC.
9 * After cold boot or da9063-induced restart, both the da9063 and da9210 seem
10 * to assert their interrupt request lines. Hence as soon as one driver
11 * requests this irq, it gets stuck in an interrupt storm, as it only manages
12 * to deassert its own interrupt request line, and the other driver hasn't
13 * installed an interrupt handler yet.
46 bool shared; /* IRQ line is shared */ member
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| /openbmc/linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
20 communication, and an interrupt controller.
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|