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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,intc-irqpin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - enum:
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
15 /* COM Temperature Sense Reset Bitfield Definitions */
21 /* COM Temperature Sense Power Down Bitfield Definitions */
27 /* COM Temperature Sense Ready Bitfield Definitions */
33 /* COM Temperature Sense Ready Latch High Bitfield Definitions */
39 /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
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/openbmc/qemu/target/hexagon/imported/
H A Dshift.idef2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
19 * S-type Instructions
26 /* NOTE: Rdd = Rs *right* shifts don't make sense */
27 /* NOTE: Rd[d] = Rs[s] *right* shifts with saturation don't make sense */
63 RSHIFTTYPES(r_nac,Rx,Rs,4_8,-,RxV,fECHO,,)
64 RSHIFTTYPES(p_nac,Rxx,Rss,8_8,-,RxxV,fECHO,,)
142 ISHIFTTYPES(r_nac,5,Rx,Rs,4_4,-,RxV,fECHO,,)
143 ISHIFTTYPES(p_nac,6,Rxx,Rss,8_8,-,RxxV,fECHO,,)
185 Q6INSN(S4_andi_##TAGEND,"Rx32=and(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)&INNERSEM;})\
186 Q6INSN(S4_ori_##TAGEND, "Rx32=or(#u8,"INNEROP")",,"Shift-op",{RxV=fIMMEXT(uiV)|INNERSEM;})\
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/openbmc/linux/drivers/irqchip/
H A Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 * (*) May be accessed by more than one driver instance - lock needed
42 * (**) Read-modify-write access by one driver instance - lock needed
43 * (***) Accessed by one driver instance only - no locking needed
50 int width; member
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/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
25 /* Bitfield operations */
27 /* Produces a mask of set bits covering a range of a 32-bit value */
28 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument
30 return ((1 << width) - 1) << shift; in bitfield_mask()
33 /* Extract the value of a bitfield found within a given register value */
34 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
36 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
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/openbmc/linux/drivers/staging/media/tegra-video/
H A Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Tegra20-specific VI implementation
14 #include <linux/bitfield.h>
19 #include <linux/v4l2-mediabus.h>
26 /* This are just good-sense numbers. The actual min/max is not documented. */
32 /* --------------------------------------------------------------------------
147 /* --------------------------------------------------------------------------
153 writel(val, chan->vi->iomem + addr); in tegra20_vi_write()
164 unsigned int input_mbus_code = chan->fmtinfo->code; in tegra20_vi_get_input_formats()
192 u32 output_fourcc = chan->format.pixelformat; in tegra20_vi_get_output_formats()
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/openbmc/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
144 #define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-hwmon16 The contents of the label are free-form.
135 this voltage channel is being used for, and user-space
137 user-space.
145 When disabled the sensor read will return -ENODATA.
147 - 1: Enable
148 - 0: Disable
253 Only makes sense if the chip supports closed-loop fan speed
263 this fan channel is being used for, and user-space doesn't.
264 In all other cases, the label is provided by user-space.
272 When disabled the sensor read will return -ENODATA.
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/openbmc/linux/drivers/gpu/drm/udl/
H A Dudl_modeset.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/bitfield.h>
120 * same actual count. This makes sense once you read above a couple of
127 while (actual_count--) { in udl_lfsr16()
151 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start; in udl_set_display_mode()
152 u16 reg03 = reg01 + mode->crtc_hdisplay; in udl_set_display_mode()
153 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start; in udl_set_display_mode()
154 u16 reg07 = reg05 + mode->crtc_vdisplay; in udl_set_display_mode()
155 u16 reg09 = mode->crtc_htotal - 1; in udl_set_display_mode()
157 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1; in udl_set_display_mode()
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/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
114 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
115 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
116 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
117 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
125 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
134 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
135 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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/openbmc/linux/include/xen/interface/
H A Dxen.h1 /* SPDX-License-Identifier: MIT */
69 /* Architecture-specific hypercall definitions. */
83 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
84 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
86 * allocated to VCPU0 but can subsequently be re-bound.
102 /* Architecture-specific VIRQ definitions. */
127 * x != 0 => PFD == x - 1
129 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
130 * -------------
138 * ptr[:2] -- Machine address of the page-table entry to modify.
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/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
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/openbmc/linux/drivers/mmc/host/
H A Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
16 #include <linux/bitfield.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
[all …]
/openbmc/qemu/include/hw/xen/interface/
H A Dxen.h1 /* SPDX-License-Identifier: MIT */
13 #include "xen-compat.h"
16 #include "arch-x86/xen.h"
18 #include "arch-arm.h"
118 /* Architecture-specific hypercall definitions. */
140 /* New event-channel and physdev hypercalls introduced in 0x00030202. */
158 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
159 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
161 * allocated to VCPU0 but can subsequently be re-bound.
178 /* Architecture-specific VIRQ definitions. */
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dadv7511-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog
22 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-dv-timings.h>
32 MODULE_PARM_DESC(debug, "debug level (0-2)");
99 /* Did we receive hotplug and rx-sense signals? */
152 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd; in to_sd()
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/openbmc/linux/include/uapi/linux/
H A Dvideodev2.h1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */
5 * Copyright (C) 1999-2012 the contributors
47 * All kernel-specific stuff were moved to media/v4l2-dev.h, so
66 #include <linux/v4l2-common.h>
67 #include <linux/v4l2-controls.h>
80 /* Four-character-code (FOURCC) */
98 buffer, top-bottom order */
99 V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */
205 /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
218 * NTSC 1953 colorspace. This only makes sense when dealing with
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/openbmc/linux/Documentation/gpu/
H A Dtodo.rst11 ----------
29 Subsystem-wide refactorings
33 ---------------------------------------------
45 --------------------------------------------------
53 non-converted driver. The "Atomic mode setting design overview" series [2]_
60 .. [1] https://blog.ffwll.ch/2014/11/atomic-modeset-support-for-kms-drivers.html
69 ---------------------------------------------------------
75 avoid confusion - the other helpers in that file are all deprecated legacy
83 ----------------------------------
88 - drm_plane_helper_funcs->atomic_check gets called for enabled or disabled
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/openbmc/linux/drivers/net/phy/
H A Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include <linux/bitfield.h>
188 /* RGMII to 1000BASE-X */
190 /* RGMII to 100BASE-FX */
347 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
411 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
426 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
476 * marvell,reg-init property stored in the of_node for the phydev.
478 * marvell,reg-init = <reg-page reg mask value>,...;
480 * There may be one or more sets of <reg-page reg mask value>:
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/openbmc/u-boot/drivers/video/
H A Dstb_truetype.h1 // stb_truetype.h - v1.08 - public domain
2 // authored from 2009-2015 by Sean Barrett / RAD Game Tools
8 // render glyphs to one-channel bitmaps with antialiasing (box filter)
11 // non-MS cmaps
14 // cleartype-style AA?
16 // optimize: build edge-list directly from curves
32 // Ivan-Assen Ivanov
51 // 1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges
52 // 1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;
54 // fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?);
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
19 #include "bitfield.h"
22 /* FIXME hack so that SA-1111.h will work [cb] */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
306 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
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/openbmc/linux/fs/ntfs/
H A Dlayout.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * layout.h - All NTFS associated on-disk structures. Part of the Linux-NTFS
6 * Copyright (c) 2001-2005 Anton Altaparmakov
71 approx. 4.7x10^21 bytes. (-; */
117 * operator! (-8
163 * been written to disk. The values 0 and -1 (ie. 0xffff) are not used. All
170 * (obviously) finish before the last le16 of the first 512-byte sector.
175 NTFS_RECORD_TYPE magic; /* A four-byte magic identifying the record
212 FILE_BadClus = 8, /* Contains all bad clusters in the non-resident
223 FILE_reserved12 = 12, /* Reserved for future use (records 12-15). */
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/bitfield.h>
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr300_reg.h95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
[all …]

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