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12

/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sc7280-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
18 const: qcom,sc7280-lpass-lpi-pinctrl
23 gpio-controller: true
25 "#gpio-cells":
[all …]
H A Dqcom,sc7280-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SC7280 TLMM block
10 - Bjorn Andersson <andersson@kernel.org>
13 Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
17 const: qcom,sc7280-pinctrl
26 interrupt-controller: true
28 '#interrupt-cells':
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 CRD board device tree source
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
18 "qcom,sc7280";
[all …]
H A Dsc7280-herobrine-crd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 CRD 3+ board device tree source
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-wcd9385.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
15 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
16 compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
27 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
28 compatible = "regulator-fixed";
[all …]
H A Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
[all …]
H A Dsc7280-herobrine-herobrine-r1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-rt5682.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
16 compatible = "google,herobrine", "qcom,sc7280";
59 clock-frequency = <400000>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&tp_int_odl>;
67 interrupt-parent = <&tlmm>;
[all …]
H A Dsc7280-herobrine-audio-rt5682-3mic.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * using rt5682 codec and having 3 dmics connected to sc7280.
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-3mic";
16 audio-routing = "VA DMIC0", "vdd-micb",
17 "VA DMIC1", "vdd-micb",
18 "VA DMIC2", "vdd-micb",
19 "VA DMIC3", "vdd-micb",
24 #address-cells = <1>;
[all …]
H A Dsc7280-idp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 IDP board device tree source (common between SKU1 and SKU2)
8 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include "sc7280.dtsi"
15 #include "sc7280-chrome-common.dtsi"
16 #include "sc7280-herobrine-lte-sku.dtsi"
25 max98360a: audio-codec-0 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&amp_en>;
[all …]
H A Dsc7280-herobrine-audio-wcd9385.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 device tree source for boards using Max98360 and wcd9385 codec
9 /* BOARD-SPECIFIC TOP LEVEL NODES */
11 compatible = "google,sc7280-herobrine";
12 model = "sc7280-wcd938x-max98360a-1mic";
14 audio-routing =
35 #address-cells = <1>;
36 #size-cells = <0>;
38 dai-link@0 {
39 link-name = "MAX98360A";
[all …]
H A Dsc7280-herobrine-audio-rt5682.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-1mic";
16 audio-routing = "Headphone Jack", "HPOL",
19 #address-cells = <1>;
20 #size-cells = <0>;
22 dai-link@0 {
23 link-name = "MAX98360";
27 sound-dai = <&lpass_cpu MI2S_SECONDARY>;
[all …]
H A Dsc7280-herobrine-evoker.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "sc7280-herobrine.dtsi"
9 #include "sc7280-herobrine-audio-rt5682-3mic.dtsi"
25 clock-frequency = <400000>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&tp_int_odl>;
33 interrupt-parent = <&tlmm>;
36 vcc-supply = <&pp3300_z1>;
38 wakeup-source;
44 clock-frequency = <400000>;
[all …]
H A Dsc7280-herobrine-zombie.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "sc7280-herobrine.dtsi"
9 #include "sc7280-herobrine-audio-rt5682.dtsi"
24 clock-frequency = <400000>;
28 compatible = "hid-over-i2c";
30 pinctrl-names = "default";
31 pinctrl-0 = <&tp_int_odl>;
33 interrupt-parent = <&tlmm>;
36 hid-descr-addr = <0x01>;
37 vdd-supply = <&pp3300_z1>;
[all …]
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
24 compatible = "google,cros-ec-pwm";
[all …]
H A Dsc7280-chrome-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 fragment for devices with Chrome bootloader
20 /delete-node/ &hyp_mem;
21 /delete-node/ &xbl_mem;
22 /delete-node/ &reserved_xbl_uefi_log;
23 /delete-node/ &sec_apps_mem;
26 reserved-memory {
29 no-map;
34 no-map;
39 no-map;
[all …]
H A Dsc7280-herobrine-villager.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "sc7280-herobrine.dtsi"
24 clock-frequency = <400000>;
27 compatible = "hid-over-i2c";
29 pinctrl-names = "default";
30 pinctrl-0 = <&tp_int_odl>;
32 interrupt-parent = <&tlmm>;
35 hid-descr-addr = <0x20>;
36 vdd-supply = <&pp3300_z1>;
38 wakeup-source;
[all …]
H A Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 Qcard device tree source
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 #include "sc7280.dtsi"
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
[all …]
H A Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7280.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
[all …]
/openbmc/linux/drivers/pinctrl/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
4 obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
5 obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
6 obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
7 obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
8 obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
9 obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
10 obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
11 obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 source "drivers/pinctrl/qcom/Kconfig.msm"
30 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
45 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
58 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
63 tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
67 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69 (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
76 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
85 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
[all …]
H A Dpinctrl-sc7280-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * ALSA SoC platform-machine driver for QTi LPASS
11 #include "pinctrl-lpass-lpi.h"
148 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
157 .name = "qcom-sc7280-lpass-lpi-pinctrl",
165 MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
H A DKconfig.msm1 # SPDX-License-Identifier: GPL-2.0-only
8 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
22 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
29 This is the pinctrl, pinmux, pinconf and gpiolib driver for
38 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
45 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
53 This is the pinctrl, pinmux, pinconf and gpiolib driver for
62 This is the pinctrl, pinmux, pinconf and gpiolib driver for
71 This is the pinctrl, pinmux, pinconf and gpiolib driver for
[all …]
H A Dpinctrl-sc7280.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "pinctrl-msm.h"
63 .mux_bit = -1, \
66 .oe_bit = -1, \
67 .in_bit = -1, \
68 .out_bit = -1, \
69 .intr_enable_bit = -1, \
70 .intr_status_bit = -1, \
71 .intr_target_bit = -1, \
72 .intr_raw_status_bit = -1, \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
[all …]

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