| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | ti,dp83867.txt | 1 * Texas Instruments - dp83867 Giga bit ethernet phy
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
14 TX/RX lanes.
15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
23 ethernet-phy@0 {
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | qcom,pmic-typec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,pmic-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC based USB Type-C block
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm PMIC Type-C block
18 - qcom,pm8150b-typec
22 $ref: /schemas/connector/usb-connector.yaml#
26 description: Type-C port and pdphy SPMI register base offsets
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| /openbmc/linux/Documentation/devicetree/bindings/serial/ |
| H A D | st,stm32-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
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| H A D | serial.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | stm32-usart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DRIVER_NAME "stm32-usart"
182 #define RX_BUF_L 4096 /* dma rx buffer length */
183 #define RX_BUF_P (RX_BUF_L / 2) /* dma rx buffer period */
184 #define TX_BUF_L RX_BUF_L /* dma tx buffer length */
192 struct dma_chan *rx_ch; /* dma rx channel */
193 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
194 unsigned char *rx_buf; /* dma rx buffer cpu address */
195 struct dma_chan *tx_ch; /* dma tx channel */
196 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | pxa168fb.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* ------------< LCD register >------------ */
177 #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */ argument
179 #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */ argument
185 #define CFG_RXBITSTO0(rx) ((rx) << 5) argument
187 #define CFG_TXBITSTO0(tx) ((tx) << 4) argument
198 /* SPI Tx Data Register */
202 1. Smart Pannel 8-bit Bus Control Register.
236 #define CFG_GRA_SWAPRB(swap) ((swap) << 12) argument
238 #define CFG_GRA_SWAPUV(swap) ((swap) << 11) argument
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| /openbmc/u-boot/include/linux/ |
| H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
52 /* Media-dependent registers. */
53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
54 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
55 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
56 * Lanes B-D are numbered 134-136. */
57 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
58 #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
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| H A D | serial_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
41 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
52 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
116 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
183 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
205 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
206 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
207 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
208 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | gpmi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
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| /openbmc/linux/drivers/staging/vt6655/ |
| H A D | card.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * s_vSafeResetTx - Rest Tx
9 * CARDvSetRSPINF - Set RSPINF
10 * CARDvUpdateBasicTopRate - Update BasicTopRate
11 * CARDbAddBasicRate - Add to BasicRateSet
12 * CARDbIsOFDMinBasicRate - Check if any OFDM rate is in BasicRateSet
13 * CARDqGetTSFOffset - Calculate TSFOffset
14 * vt6655_get_current_tsf - Read Current NIC TSF counter
15 * CARDqGetNextTBTT - Calculate Next Beacon TSF counter
16 * CARDvSetFirstNextTBTT - Set NIC Beacon time
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| /openbmc/linux/include/uapi/linux/ |
| H A D | serial_reg.h | 1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
44 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
60 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
131 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
141 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
199 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
221 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
222 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
223 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
224 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
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| H A D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
62 * Lanes B-D are numbered 134-136. */
63 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
64 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
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| /openbmc/linux/drivers/net/ethernet/sun/ |
| H A D | sunqe.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
49 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
51 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
56 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
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| /openbmc/qemu/hw/net/ |
| H A D | e1000_regs.h | 4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
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| /openbmc/linux/arch/mips/include/asm/sgi/ |
| H A D | hpc3.h | 22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
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| /openbmc/linux/drivers/net/wireless/broadcom/b43/ |
| H A D | phy_n.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
57 #define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
| H A D | ns2-svk.dts | 33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
120 pl022,rx-level-trig = <1>;
121 pl022,tx-level-trig = <1>;
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| /openbmc/linux/drivers/net/ethernet/sfc/ |
| H A D | efx_channels.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
99 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
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| /openbmc/linux/drivers/net/wireless/ath/ath12k/ |
| H A D | ce.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
12 /* Byte swap data words */
21 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
29 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
31 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
36 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
37 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
83 /* #entries in source ring - Must be a power of 2 */
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| /openbmc/linux/drivers/net/wireless/ath/ath11k/ |
| H A D | ce.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
12 /* Byte swap data words */
25 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
36 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
38 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
43 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
44 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
108 /* #entries in source ring - Must be a power of 2 */
117 /* #entries in destination ring - Must be a power of 2 */
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| /openbmc/linux/drivers/net/ethernet/sfc/siena/ |
| H A D | efx_channels.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
100 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
110 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
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| /openbmc/linux/drivers/net/ethernet/amazon/ena/ |
| H A D | ena_admin_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
119 * 1 : ctrl_data - control buffer address valid
120 * 2 : ctrl_data_indirect - control buffer address
142 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
193 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
199 /* 3:0 : placement_policy - Describing where the SQ
201 * 0x1 - descriptors and headers are in OS memory,
202 * 0x3 - descriptors and headers in device memory
204 * 6:4 : completion_policy - Describing what policy
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| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_sai.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #include "imx-pcm.h"
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
56 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
59 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
66 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
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