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Searched +full:rx +full:- +full:clk +full:- +full:delay +full:- +full:ps (Results 1 – 25 of 70) sorted by relevance

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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
56 * input RX rising/falling edge and sent to the Ethernet internals. This sets
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
[all …]
H A Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
[all …]
H A Ddwmac-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
9 #include <linux/clk.h>
75 struct ingenic_mac *mac = plat_dat->bsp_priv; in ingenic_mac_init()
78 if (mac->soc_info->set_mode) { in ingenic_mac_init()
79 ret = mac->soc_info->set_mode(plat_dat); in ingenic_mac_init()
89 struct ingenic_mac *mac = plat_dat->bsp_priv; in jz4775_mac_set_mode()
92 switch (plat_dat->mac_interface) { in jz4775_mac_set_mode()
96 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); in jz4775_mac_set_mode()
102 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n"); in jz4775_mac_set_mode()
[all …]
H A Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
44 * @rx_delay_max: Maximum raw value for RX delay chain
45 * @tx_delay_max: Maximum raw value for TX delay chain
47 * the RX and TX delay chain registers. A
61 /* struct sunxi_priv_data - hold all sunxi private data
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
25 - nxp,sja1105r
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
95 /* Rx Error Counter Register */
104 /* FIBER Auto-Negotiation link partner ability */
122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
126 * TX Fast-E Delay is bits 15:12, default 0xf
[all …]
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
29 #include <linux/clk.h>
30 #include <linux/delay.h>
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
260 /* Delay used to get the second part from the LTC */
317 /* Lock for Rx ts fifo */
429 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
433 if (type && type->interrupt_level_mask) in kszphy_config_intr()
434 mask = type->interrupt_level_mask; in kszphy_config_intr()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Dam335x-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "ti,am335x-evm", "ti,am33xx";
16 cpu0-supply = <&vdd1_reg>;
26 stdout-path = &uart0;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
[all …]
H A Dam335x-cm-t335.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335
5 * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "CompuLab CM-T335";
15 compatible = "compulab,cm-t335", "ti,am33xx";
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&gpio_led_pins>;
[all …]
/openbmc/linux/drivers/input/serio/
H A Dps2-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO based serio bus driver for bit banging the PS/2 protocol
5 * Author: Danilo Krummrich <danilokrummrich@dk-develop.de>
21 #include <linux/delay.h>
24 #define DRIVER_NAME "ps2-gpio"
50 * interrupt interval should be ~60us. Let's allow +/- 20us for frequency
61 * |-----------------| |--------|
68 #define PS2_IRQ_MIN_INTERVAL_US (PS2_CLK_MIN_INTERVAL_US - 20)
84 } rx; member
98 struct ps2_gpio_data *drvdata = serio->port_data; in ps2_gpio_open()
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 #include <linux/clk.h>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
308 * the RX side. Those two bytes being at the front of the Ethernet
336 /* Max number of Rx descriptors */
374 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
377 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dmxic_nand.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
15 #include <linux/mtd/nand-ecc-sw-hamming.h>
73 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
174 struct clk *ps_clk;
175 struct clk *send_clk;
176 struct clk *send_dly_clk;
188 ret = clk_prepare_enable(nfc->ps_clk); in mxic_nfc_clk_enable()
192 ret = clk_prepare_enable(nfc->send_clk); in mxic_nfc_clk_enable()
196 ret = clk_prepare_enable(nfc->send_dly_clk); in mxic_nfc_clk_enable()
[all …]
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
14 #include <linux/delay.h>
33 * [11] mipi divider clk selection.
52 /* [31] clk lane tx_hs_en control selection.
53 * 1: from register. 0: use clk lane state machine.
55 * [29] clk lane tx_lp_en contrl selection.
56 * 1: from register. 0: from clk lane state machine.
88 * [4] clk chan power down. this bit is also used as the power down
97 /* [24] rx turn watch dog triggered.
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779g0-white-hawk-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
16 compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
25 stdout-path = "serial0:921600n8";
29 compatible = "gpio-keys";
31 pinctrl-0 = <&keys_pins>;
32 pinctrl-names = "default";
34 key-1 {
[all …]
H A Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
226 readl_relaxed((port)->regs + SPI_##reg)
228 writel_relaxed((value), (port)->regs + SPI_##reg)
230 writew_relaxed((value), (port)->regs + SPI_##reg)
[all …]

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