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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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H A Dnxp,pca9685-pwm.txt1 NXP PCA9685 16-channel 12-bit PWM LED controller
5 - compatible: "nxp,pca9685-pwm"
6 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
8 The index 16 is the ALLCALL channel, that sets all PWM channels at the same
12 - invert (bool): boolean to enable inverted logic
13 - open-drain (bool): boolean to configure outputs with open-drain structure;
14 if omitted use totem-pole structure
22 compatible = "nxp,pca9685-pwm";
23 #pwm-cells = <2>;
26 open-drain;
/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
47 and PWM output control functions. Using this parameter
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
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H A Dmax31790.rst10 Addresses scanned: -
18 -----------
23 PWM outputs. The desired fan speeds (or PWM duty cycles) are written
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
30 Six pins are dedicated tachometer inputs. Any of the six PWM outputs can
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
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H A Dlm85.rst79 - Philip Pokorny <ppokorny@penguincomputing.com>,
80 - Frodo Looijaard <frodol@dds.nl>,
81 - Richard Barrington <rich_b_nz@clear.net.nz>,
82 - Margit Schubert-While <margitsw@t-online.de>,
83 - Justin Thiessen <jthiessen@penguincomputing.com>
86 -----------
92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
94 temperatures and five (5) voltages. It has four (4) 16-bit counters for
96 VID signals from the processor to the VRM. Lastly, there are three (3) PWM
97 outputs that can be used to control fan speed.
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H A Dadt7470.rst17 -----------
22 The ADT7470 uses the 2-wire interface compatible with the SMBus 2.0
24 external temperatures. It has four (4) 16-bit counters for measuring fan speed.
25 There are four (4) PWM outputs that can be used to control fan speed.
27 A sophisticated control system for the PWM outputs is designed into the ADT7470
29 temperature sensors. Each PWM output is individually adjustable and
30 programmable. Once configured, the ADT7470 will adjust the PWM outputs in
32 feature can also be disabled for manual control of the PWM's.
40 automatic fan pwm control to set the fan speed. The driver will not read the
45 ----------------
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H A Dadt7475.rst39 - Jordan Crouse
40 - Hans de Goede
41 - Darrick J. Wong (documentation)
42 - Jean Delvare
46 -----------
56 The ADT747x uses the 2-wire interface compatible with the SMBus 2.0
58 temperatures and two (2) or more voltages. It has four (4) 16-bit counters
59 for measuring fan speed. There are three (3) PWM outputs that can be used
62 A sophisticated control system for the PWM outputs is designed into the
64 three temperature sensors. Each PWM output is individually adjustable and
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H A Dadt7462.rst17 -----------
27 A sophisticated control system for the PWM outputs is designed into the ADT7462
29 temperature sensors. Each PWM output is individually adjustable and
30 programmable. Once configured, the ADT7462 will adjust the PWM outputs in
32 feature can also be disabled for manual control of the PWM's.
43 ----------------
45 The ADT7462 have a 10-bit ADC and can therefore measure temperatures
49 determining an optimal configuration for the automatic PWM control.
55 -------------------
59 * PWM Control
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H A Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
42 data sheet. Our temperature reports and fan PWM outputs are very smooth
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H A Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
49 can be configured to PWM output or Analogue DC output via their associated
50 pwmX_mode. Outputs pwm4 through pwm7 may or may not be present depending on
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
116 ----------------
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H A Dw83793.rst10 Addresses scanned: I2C 0x2c - 0x2f
15 - Yuan Mu (Winbond Electronics)
16 - Rudolf Marek <r.marek@assembler.cz>
20 -----------------
36 -----------
42 6 remote temperatures, up to 8 sets of PWM fan controls, SmartFan
43 (automatic fan speed control) on all temperature/PWM combinations, 2
44 sets of 6-pin CPU VID input.
48 voltage0-2 is 2mV, resolution of voltage3/4/5 is 16mV, 8mV for voltage6,
49 24mV for voltage7/8. Temp1-4 have a 0.25 degree Celsius resolution,
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H A Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
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H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
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/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dnpcm750-pwm-fan.txt1 Nuvoton NPCM PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
4 controller outputs and 16 Fan tachometer controller inputs.
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
7 controller outputs and 16 Fan tachometer controller inputs.
9 Required properties for pwm-fan node
10 - #address-cells : should be 1.
11 - #size-cells : should be 0.
12 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
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H A Daspeed,g6-pwm-tach.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ASPEED G6 PWM and Fan Tach controller
11 - Billy Tsai <billy_tsai@aspeedtech.com>
14 The ASPEED PWM controller can support up to 16 PWM outputs.
22 - aspeed,ast2600-pwm-tach
33 "#pwm-cells":
37 "^fan-[0-9]+$":
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/openbmc/entity-manager/configurations/
H A Dr2000_chassis.json243 "Outputs": [ array
244 "Pwm 1"
269 "Outputs": [ array
270 "Pwm 2"
295 "Outputs": [ array
296 "Pwm 3"
321 "Outputs": [ array
322 "Pwm 4"
347 "Outputs": [ array
348 "Pwm 5"
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H A Dr1000_chassis.json329 "ICoefficient": -4.64,
339 "Outputs": [], array
340 "PCoefficient": -0.15,
343 "SlewNeg": -1,
370 "Outputs": [ array
371 "Pwm 1"
397 "Outputs": [ array
398 "Pwm 2"
424 "Outputs": [ array
425 "Pwm 3"
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H A Dwft_baseboard.json545 "Pwm": 0, number
556 "Pwm": 1, number
567 "Pwm": 2, number
578 "Pwm": 3, number
589 "Pwm": 4, number
600 "Pwm": 5, number
611 "Pwm": 0, number
621 "Pwm": 1, number
631 "Pwm": 2, number
641 "Pwm": 3, number
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H A Dsolum_pssf162202_psu.json24 "Outputs": [ array
25 "Pwm PSU$ADDRESS % 4 + 1 Fan 1"
50 "Outputs": [ array
51 "Pwm PSU$ADDRESS % 4 + 1 Fan 2"
66 "ICoefficient": -4.64,
76 "Outputs": [], array
77 "PCoefficient": -0.15,
80 "SlewNeg": -1,
/openbmc/openbmc/meta-amd/meta-ethanolx/recipes-phosphor/configuration/entity-manager/
H A Dethanolx-baseboard.json5 "Pwm" : 0, number
11 "Pwm" : 1, number
17 "Pwm" : 2, number
23 "Pwm" : 3, number
29 "Pwm" : 4, number
35 "Pwm" : 5, number
41 "Pwm" : 6, number
47 "Pwm" : 7, number
1174 "Outputs": [ array
1175 "Pwm 1"
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/openbmc/linux/drivers/pwm/
H A Dpwm-lp3943.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI/National Semiconductor LP3943 PWM driver
15 #include <linux/pwm.h>
36 struct lp3943_platform_data *pdata = lp3943_pwm->pdata; in lp3943_pwm_request_map()
37 struct lp3943 *lp3943 = lp3943_pwm->lp3943; in lp3943_pwm_request_map()
43 return ERR_PTR(-ENOMEM); in lp3943_pwm_request_map()
45 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
46 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
48 for (i = 0; i < pwm_map->num_outputs; i++) { in lp3943_pwm_request_map()
49 offset = pwm_map->output[i]; in lp3943_pwm_request_map()
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/openbmc/openbmc/meta-amd/meta-daytonax/recipes-phosphor/configuration/entity-manager/
H A Ddaytonax-baseboard.json5 "Pwm" : 0, number
11 "Pwm" : 1, number
17 "Pwm" : 2, number
23 "Pwm" : 3, number
29 "Pwm" : 4, number
35 "Pwm" : 5, number
1587 "Outputs": [ array
1588 "Pwm PSU0 Fan 1"
1603 "ICoefficient": -4.64,
1613 "Outputs": [], array
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/openbmc/u-boot/drivers/pwm/
H A DKconfig2 bool "Enable support for pulse-width modulation devices (PWM)"
5 A pulse-width modulator emits a pulse of varying width and provides
7 is often used to control a voltage level. The more time the PWM
8 spends in the 'high' state, the higher the voltage. The PWM's
13 bool "Enable support for the Exynos PWM"
16 This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
17 supports a programmable period and duty cycle. A 32-bit counter is
22 bool "Enable support for the Rockchip PWM"
25 This PWM is found on RK3288 and other Rockchip SoCs. It supports a
26 programmable period and duty cycle. A 32-bit counter is used.
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