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/openbmc/linux/Documentation/devicetree/bindings/devfreq/event/
H A Dsamsung,exynos-ppmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
15 each IP. PPMU provides the primitive values to get performance data. These
16 PPMU events provide information of the SoC's behaviors so that you may use to
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/openbmc/linux/arch/powerpc/perf/
H A Dcore-book3s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
19 #include <asm/code-patching.h>
39 struct perf_event *event[MAX_HWEVENTS]; member
66 static struct power_pmu *ppmu; variable
78 * 32-bit doesn't have MMCRA but does have an MMCR2,
80 * Also 32-bit doesn't have MMCR3, SIER2 and SIER3.
82 * these registers (via mtspr/mfspr) are done under ppmu flag
84 * for 32-bit.
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H A Dcore-fsl-emb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - Freescale Embedded Performance Monitor
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
23 struct perf_event *event[MAX_HWEVENTS]; member
27 static struct fsl_emb_pmu *ppmu; variable
162 static void fsl_emb_pmu_read(struct perf_event *event) in fsl_emb_pmu_read() argument
166 if (event->hw.state & PERF_HES_STOPPED) in fsl_emb_pmu_read()
171 * are soft-disabled, as long as interrupts are hard-enabled. in fsl_emb_pmu_read()
175 prev = local64_read(&event->hw.prev_count); in fsl_emb_pmu_read()
177 val = read_pmc(event->hw.idx); in fsl_emb_pmu_read()
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-ppmu-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree sources for Exynos4412 PPMU common device tree
13 ppmu_dmc0_3: ppmu-event3-dmc0 {
14 event-name = "ppmu-event3-dmc0";
23 ppmu_dmc1_3: ppmu-event3-dmc1 {
24 event-name = "ppmu-event3-dmc1";
33 ppmu_leftbus_3: ppmu-event3-leftbus {
34 event-name = "ppmu-event3-leftbus";
43 ppmu_rightbus_3: ppmu-event3-rightbus {
44 event-name = "ppmu-event3-rightbus";
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/openbmc/linux/drivers/devfreq/event/
H A Dexynos-ppmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * exynos_ppmu.c - Exynos PPMU (Platform Performance Monitoring Unit) support
5 * Copyright (c) 2014-2015 Samsung Electronics Co., Ltd.
20 #include <linux/devfreq-event.h>
22 #include "exynos-ppmu.h"
41 struct exynos_ppmu_data ppmu; member
46 { "ppmu-event0-"#name, PPMU_PMNCNT0 }, \
47 { "ppmu-event1-"#name, PPMU_PMNCNT1 }, \
48 { "ppmu-event2-"#name, PPMU_PMNCNT2 }, \
49 { "ppmu-event3-"#name, PPMU_PMNCNT3 }
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
18 tristate "Exynos NoC (Network On Chip) Probe DEVFREQ event Driver"
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
27 tristate "Exynos PPMU (Platform Performance Monitoring Unit) DEVFREQ event Driver"
31 This add the devfreq-event driver for Exynos SoC. It provides PPMU
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 # Exynos DEVFREQ Event Drivers
4 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP) += exynos-nocp.o
5 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
6 obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
H A Dexynos-ppmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * exynos_ppmu.h - Exynos PPMU header file
50 /* Cycle Counter and Performance Event Counter Register */
58 /* Bus Event Generator */
118 /* Cycle Counter and Performance Event Counter Register */
126 /* Bus Event Generator */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsamsung,exynos5422-dmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Lukasz Luba <lukasz.luba@arm.com>
19 controller in runtime, the driver uses the PPMU (Platform Performance
27 - const: samsung,exynos5422-dmc
29 clock-names:
31 - const: fout_spll
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgf119.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
45 { -1, gf100_pmu_nofw, &gf119_pmu },
51 struct nvkm_pmu **ppmu) in gf119_pmu_new() argument
53 return nvkm_pmu_new_(gf119_pmu_fwif, device, type, inst, ppmu); in gf119_pmu_new()
H A Dgk208.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
46 { -1, gf100_pmu_nofw, &gk208_pmu },
52 struct nvkm_pmu **ppmu) in gk208_pmu_new() argument
54 return nvkm_pmu_new_(gk208_pmu_fwif, device, type, inst, ppmu); in gk208_pmu_new()
H A Dgm107.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47 { -1, gf100_pmu_nofw, &gm107_pmu },
53 struct nvkm_pmu **ppmu) in gm107_pmu_new() argument
55 return nvkm_pmu_new_(gm107_pmu_fwif, device, type, inst, ppmu); in gm107_pmu_new()
H A Dgp102.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
49 { -1, gm200_pmu_nofw, &gp102_pmu },
55 struct nvkm_pmu **ppmu) in gp102_pmu_new() argument
57 return nvkm_pmu_new_(gp102_pmu_fwif, device, type, inst, ppmu); in gp102_pmu_new()
H A Dgf100.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
32 struct nvkm_device *device = pmu->subdev.device; in gf100_pmu_reset()
40 return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU, 0); in gf100_pmu_enabled()
67 { -1, gf100_pmu_nofw, &gf100_pmu },
73 struct nvkm_pmu **ppmu) in gf100_pmu_new() argument
75 return nvkm_pmu_new_(gf100_pmu_fwif, device, type, inst, ppmu); in gf100_pmu_new()
H A Dbase.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
32 struct nvkm_pmu *pmu = device->pmu; in nvkm_pmu_fan_controlled()
37 if (pmu && pmu->func->code.size) in nvkm_pmu_fan_controlled()
40 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi in nvkm_pmu_fan_controlled()
44 return (device->chipset >= 0xc0); in nvkm_pmu_fan_controlled()
50 if (pmu && pmu->func->pgob) in nvkm_pmu_pgob()
51 pmu->func->pgob(pmu, enable); in nvkm_pmu_pgob()
58 return pmu->func->recv(pmu); in nvkm_pmu_recv()
65 if (!pmu || !pmu->func->send) in nvkm_pmu_send()
66 return -ENODEV; in nvkm_pmu_send()
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H A Dgp10b.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
35 return msg->falcon_mask; in gp10b_pmu_acr_bootstrap_multiple_falcons_cb()
52 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gp10b_pmu_acr_bootstrap_multiple_falcons()
54 &pmu->subdev, msecs_to_jiffies(1000)); in gp10b_pmu_acr_bootstrap_multiple_falcons()
57 ret = -EIO; in gp10b_pmu_acr_bootstrap_multiple_falcons()
87 { -1, gm200_pmu_nofw, &gm20b_pmu },
93 struct nvkm_pmu **ppmu) in gp10b_pmu_new() argument
95 return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu); in gp10b_pmu_new()
H A Dgm200.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
70 nvkm_warn(&pmu->subdev, "firmware unavailable\n"); in gm200_pmu_nofw()
76 { -1, gm200_pmu_nofw, &gm200_pmu },
82 struct nvkm_pmu **ppmu) in gm200_pmu_new() argument
84 return nvkm_pmu_new_(gm200_pmu_fwif, device, type, inst, ppmu); in gm200_pmu_new()
H A Dgk110.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
34 struct nvkm_device *device = pmu->subdev.device; in gk110_pmu_pgob()
104 { -1, gf100_pmu_nofw, &gk110_pmu },
110 struct nvkm_pmu **ppmu) in gk110_pmu_new() argument
112 return nvkm_pmu_new_(gk110_pmu_fwif, device, type, inst, ppmu); in gk110_pmu_new()
H A Dgk104.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41 while (size--) in magic_()
59 struct nvkm_device *device = pmu->subdev.device; in gk104_pmu_pgob()
61 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) in gk104_pmu_pgob()
84 if (nvkm_boolopt(device->cfgopt, "War00C800_0", true)) { in gk104_pmu_pgob()
85 switch (device->chipset) { in gk104_pmu_pgob()
125 { -1, gf100_pmu_nofw, &gk104_pmu },
131 struct nvkm_pmu **ppmu) in gk104_pmu_new() argument
133 return nvkm_pmu_new_(gk104_pmu_fwif, device, type, inst, ppmu); in gk104_pmu_new()
H A Dgk20a.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_target()
61 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_cur_state()
63 *state = clk->pstate; in gk20a_pmu_dvfs_get_cur_state()
70 struct gk20a_pmu_dvfs_data *data = pmu->data; in gk20a_pmu_dvfs_get_target_state()
71 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_target_state()
75 level = cur_level = clk->pstate; in gk20a_pmu_dvfs_get_target_state()
77 if (load > data->p_load_max) { in gk20a_pmu_dvfs_get_target_state()
78 level = min(clk->state_nr - 1, level + (clk->state_nr / 3)); in gk20a_pmu_dvfs_get_target_state()
80 level += ((load - data->p_load_target) * 10 / in gk20a_pmu_dvfs_get_target_state()
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H A Dgm20b.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
35 return msg->falcon_id; in gm20b_pmu_acr_bootstrap_falcon_cb()
52 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_bootstrap_falcon()
54 &pmu->subdev, msecs_to_jiffies(1000)); in gm20b_pmu_acr_bootstrap_falcon()
57 ret = -EIO; in gm20b_pmu_acr_bootstrap_falcon()
71 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_pmu_acr_bld_patch()
81 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_pmu_acr_bld_patch()
83 loader_config_dump(&acr->subdev, &hdr); in gm20b_pmu_acr_bld_patch()
90 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gm20b_pmu_acr_bld_write()
91 const u64 code = (base + lsfw->app_resident_code_offset) >> 8; in gm20b_pmu_acr_bld_write()
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/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
18 monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
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/openbmc/linux/include/dt-bindings/pmu/
H A Dexynos_ppmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Samsung Exynos PPMU event types for counting in regs
/openbmc/linux/drivers/devfreq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 to a device by 1-to-1. The device registering devfreq takes the
39 Simple-Ondemand should be able to provide busy/total counter
89 PPMU counters of memory controllers by using DEVFREQ-event device
153 source "drivers/devfreq/event/Kconfig"

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