Searched full:pllp_out2 (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra20-pinmux.yaml | 64 pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 931 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
962 * NOTE: If you want to change PLLP_OUT2 away from 204MHz, in tegra210_setup_pllp()
964 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz. in tegra210_setup_pllp()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | pinmux.c | 291 PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 560 * not applied. pllP_out2 does have divp applied. All other pllP_outN in clock_get_rate()
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| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra20.c | 1927 FUNCTION(pllp_out2),
2054 MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 3415 /* PLLP_OUT2 */ in tegra210_pll_init()
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