| /openbmc/linux/include/linux/platform_data/ |
| H A D | si5351.h | 89 * @pll_reset: if true, clkout can reset its pll
99 bool pll_reset; member
108 * @pll_reset: array indicating if plls should be reset after setting the rate
113 bool pll_reset[2]; member
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| /openbmc/linux/drivers/usb/host/ |
| H A D | ehci-fsl.h | 49 #define PLL_RESET (1<<8) macro
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 79 PLL_RESET = 1, enumerator
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-si5351.c | 523 if (pdata->pll_reset[hwdata->num]) in si5351_pll_set_rate()
950 if (pdata->clkout[hwdata->num].pll_reset) in si5351_clkout_prepare()
1236 pdata->pll_reset[0] = true; in si5351_dt_parse()
1237 pdata->pll_reset[1] = true; in si5351_dt_parse()
1261 pdata->pll_reset[num] = true; in si5351_dt_parse()
1265 pdata->pll_reset[num] = false; in si5351_dt_parse()
1390 pdata->clkout[num].pll_reset = in si5351_dt_parse()
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,qcm2290-tlmm.yaml | 77 pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3,
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| H A D | qcom,sdm670-tlmm.yaml | 89 pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
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| H A D | qcom,sm6115-tlmm.yaml | 82 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
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| H A D | qcom,sm8250-pinctrl.yaml | 88 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
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| H A D | qcom,sm7150-tlmm.yaml | 93 pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
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| H A D | qcom,sm6375-tlmm.yaml | 98 phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
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| H A D | qcom,sc7180-pinctrl.yaml | 94 pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
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| H A D | qcom,sc8180x-tlmm.yaml | 95 pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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| H A D | qcom,sm6125-tlmm.yaml | 95 nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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| H A D | qcom,sdm845-pinctrl.yaml | 92 pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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| H A D | qcom,sm6350-tlmm.yaml | 100 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,
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| H A D | qcom,sm8150-pinctrl.yaml | 93 pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
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| H A D | qcom,sc7280-pinctrl.yaml | 103 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
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| H A D | qcom,msm8998-pinctrl.yaml | 100 pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
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| H A D | qcom,sdx65-tlmm.yaml | 75 pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
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| H A D | qcom,msm8996-pinctrl.yaml | 84 qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4,
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| H A D | qcom,sdm630-pinctrl.yaml | 111 phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | dibx000_common.h | 122 u8 pll_reset; member
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| /openbmc/qemu/hw/misc/ |
| H A D | bcm2835_cprman.c | 56 static void pll_reset(DeviceState *dev) in pll_reset() function
138 device_class_set_legacy_reset(dc, pll_reset); in pll_class_init()
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| /openbmc/u-boot/include/usb/ |
| H A D | ehci-ci.h | 51 #define PLL_RESET (1 << 8) macro
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| /openbmc/linux/drivers/media/usb/dvb-usb/ |
| H A D | dib0700_devices.c | 227 .pll_reset = 1,
393 .pll_reset = 1,
662 .pll_reset = 1,
954 .pll_reset = 1,
1180 .pll_reset = 1,
1519 .pll_reset = 1,
1956 .pll_reset = 0,
2781 .pll_reset = 0,
3564 .pll_reset = 1,
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