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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll5-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h25 u32 pll5_cfg; /* 0x20 pll5 ddr control */
99 u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */
113 u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/
118 u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */
254 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
H A Dclock_sun4i.h22 u32 pll5_cfg; /* 0x20 pll5 control */
23 u32 pll5_tun; /* 0x24 pll5 tuning */
27 u32 pll1_tun2; /* 0x34 pll5 tuning2 */
29 u32 pll5_tun2; /* 0x3c pll5 tuning2 */
H A Dclock_sun50i_h6.h15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
35 u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
59 u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
233 /* pll5 bit field */
H A Dclock_sun6i.h22 u32 pll5_cfg; /* 0x20 pll5 control */
134 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
142 u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
148 u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
397 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
/openbmc/qemu/hw/misc/
H A Dallwinner-a10-ccm.c39 REG_PLL5_CFG = 0x0020, /* PLL5 Control */
40 REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */
45 REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */
/openbmc/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a779a0-cpg-mssr.c72 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
246 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
257 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a779g0-cpg-mssr.c74 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
259 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Drzg2l-cpg.c98 * @mux_dsi_div_params: pll5 mux and dsi div parameters
572 * OSC --> PLL5 --> FOUTPOSTDIV-->| in rzg2l_cpg_sipll5_set_rate()
577 * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates in rzg2l_cpg_sipll5_set_rate()
580 * OSC --> PLL5 --> FOUTPOSTDIV in rzg2l_cpg_sipll5_set_rate()
590 /* Put PLL5 into standby mode */ in rzg2l_cpg_sipll5_set_rate()
595 dev_err(priv->dev, "failed to release pll5 lock"); in rzg2l_cpg_sipll5_set_rate()
622 dev_err(priv->dev, "failed to lock pll5"); in rzg2l_cpg_sipll5_set_rate()
/openbmc/u-boot/board/aristainetos/
H A Daristainetos-v2.c410 /* set PLL5 clock */ in enable_lvds()
415 /* set PLL5 to 232720000Hz */ in enable_lvds()
441 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ in enable_lvds()
503 /* set PLL5 to 197994996Hz */ in enable_spi_display()
529 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ in enable_spi_display()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c557 debug("pll5 div = %d, num = %d, denom = %d\n", in enable_pll_video()
560 /* Power up PLL5 video */ in enable_pll_video()
594 /* Wait PLL5 lock */ in enable_pll_video()
607 puts("Lock PLL5 timeout\n"); in enable_pll_video()
715 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
729 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
751 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
1351 /* Disable PLL5 */ in disable_ldb_di_clock_sources()
1376 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
/openbmc/linux/Documentation/devicetree/bindings/mips/
H A Dmscc.txt48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
/openbmc/linux/drivers/clk/mmp/
H A Dclk-of-pxa1928.c41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c781 debug("pll5 div = %d, num = %d, denom = %d\n", in enable_pll_video()
784 /* Power up PLL5 video and disable its output */ in enable_pll_video()
834 /* Wait PLL5 lock */ in enable_pll_video()
847 printf("Lock PLL5 timeout\n"); in enable_pll_video()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun8i_a83t.c113 /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ in clock_set_pll5()
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h258 #define PLL5 249 macro
H A Dqcom,gcc-mdm9615.h291 #define PLL5 281 macro
H A Dqcom,gcc-msm8960.h289 #define PLL5 281 macro

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