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/openbmc/qemu/hw/intc/
H A Dsifive_plic.c2 * SiFive PLIC (Platform Level Interrupt Controller)
6 * This provides a parameterizable interrupt controller based on SiFive's PLIC.
25 #include "qemu/error-report.h"
28 #include "hw/qdev-properties.h"
37 return addr >= base && addr - base < num; in addr_between()
47 error_report("plic: invalid mode '%c'", c); in char_to_mode()
48 exit(1); in char_to_mode()
65 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_pending() argument
67 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); in sifive_plic_set_pending()
70 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_claimed() argument
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
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H A Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
23 interrupt-parent = <&plic>;
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H A Dmpfs-polarberry-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
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H A Dmpfs-m100pfs-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
18 compatible = "microchip,pcie-host-1.0";
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/openbmc/qemu/hw/riscv/
H A Dopentitan.c2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
25 #include "qemu/error-report.h"
85 if (machine->ram_size != mc->default_ram_size) { in opentitan_machine_init()
86 char *sz = size_to_str(mc->default_ram_size); in opentitan_machine_init()
93 object_initialize_child(OBJECT(machine), "soc", &s->soc, in opentitan_machine_init()
95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in opentitan_machine_init()
98 memmap[IBEX_DEV_RAM].base, machine->ram); in opentitan_machine_init()
100 if (machine->firmware) { in opentitan_machine_init()
102 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); in opentitan_machine_init()
105 if (machine->kernel_filename) { in opentitan_machine_init()
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H A Dmicrochip_pfsoc.c2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
12 * 1) PLIC (Platform Level Interrupt Controller)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
59 * See https://github.com/polarfire-soc/hart-software-services
74 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
76 * https://www.microsemi.com/document-portal/doc_download/
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
81 * https://www.microsemi.com/document-portal/doc_download/
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H A Dsifive_e.c2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
33 #include "qemu/error-report.h"
82 if (machine->ram_size != mc->default_ram_size) { in sifive_e_machine_init()
83 char *sz = size_to_str(mc->default_ram_size); in sifive_e_machine_init()
90 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); in sifive_e_machine_init()
91 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in sifive_e_machine_init()
95 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
100 if (s->revb) { in sifive_e_machine_init()
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H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
92 #define OTP_SERIAL 1
99 uint64_t mem_size = ms->ram_size; in create_fdt()
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
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/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/openbmc/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
27 mmu-type = "riscv,sv39";
28 i-cache-size = <0x8000>;
29 i-cache-line-size = <0x40>;
30 d-cache-size = <0x8000>;
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/openbmc/linux/drivers/irqchip/
H A Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "plic: " fmt
24 * This driver implements a version of the RISC-V PLIC with the actual layout
27 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
30 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
96 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
106 raw_spin_lock(&handler->enable_lock); in plic_toggle()
107 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
108 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
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/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dmicrochip,mpfs-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
14 - $ref: can-controller.yaml#
18 const: microchip,mpfs-can
21 maxItems: 1
24 maxItems: 1
27 maxItems: 1
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
17 - $ref: spi-controller.yaml#
22 - items:
23 - const: microchip,mpfs-qspi
24 - const: microchip,coreqspi-rtl-v2
25 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI
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/openbmc/u-boot/doc/
H A DREADME.AX251 AX25 is Andes CPU IP to adopt RISC-V architecture.
7 - 5-stage in-order execution pipeline
8 - Hardware Multiplier
9 - radix-2/radix-4/radix-16/radix-256/fast
10 - Hardware Divider
11 - Optional branch prediction
12 - Machine mode and optional user mode
13 - Optional performance monitoring
16 - RV64I base integer instructions
17 - RVC for 16-bit compressed instructions
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,mpfs-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: usb-drd.yaml#
13 - Conor Dooley <conor.dooley@microchip.com>
18 - microchip,mpfs-musb
23 maxItems: 1
29 interrupt-names:
31 - const: dma
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
24 maxItems: 1
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/openbmc/linux/arch/m68k/include/asm/
H A Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
104 #define MCF_IRQ_TIMER1 69 /* Timer 1 */
109 #define MCF_IRQ_UART1 74 /* UART 1 */
110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
19 - const: sifive,gpio0
22 maxItems: 1
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H A Dmicrochip,mpfs-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
15 - enum:
16 - microchip,mpfs-gpio
19 maxItems: 1
24 minItems: 1
27 interrupt-controller: true
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
29 - enum:
30 - sifive,fu540-c000-pwm
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