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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
24 mpp0 0 gpio, nand(io2), spi(cs)
[all …]
H A Dqcom,msm8960-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8960-pinctrl
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
[all …]
H A Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8192 Pin controller is used to control SoC pins.
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-388-clearfog.dts11 * This file is dual-licensed: you can use it either under the terms
49 /dts-v1/;
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
53 #include "armada-38x-solidrun-microsom.dtsi"
57 compatible = "solidrun,clearfog-a1", "marvell,armada388",
61 /* So that mvebu u-boot can update the MAC addresses */
71 stdout-path = "serial0:115200n8";
74 reg_3p3v: regulator-3p3v {
[all …]
/openbmc/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-suniv-f1c100s.c2 * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
12 * Copyright (C) 2014 Chen-Yu Tsai
14 * Chen-Yu Tsai <wens@csie.org>
18 * Maxime Ripard <maxime.ripard@free-electrons.com>
30 #include "pinctrl-sunxi.h"
38 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
45 SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
53 SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
70 SUNXI_FUNCTION(0x6, "spi1")), /* CS */
78 SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
[all …]
H A Dpinctrl-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "pinctrl-sunxi.h"
21 SUNXI_FUNCTION(0x3, "spi2"), /* CS */
28 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
35 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
110 SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
128 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
170 SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
271 SUNXI_FUNCTION(0x4, "spi1"), /* CS */
277 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
[all …]
H A Dpinctrl-sun50i-h5.c6 * Based on pinctrl-sun8i-h3.c, which is:
9 * Based on pinctrl-sun8i-a23.c, which is:
10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
23 #include "pinctrl-sunxi.h"
69 SUNXI_FUNCTION(0x2, "sim"), /* CLK */
101 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
107 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
113 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
136 SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
[all …]
H A Dpinctrl-sun8i-h3.c6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
66 SUNXI_FUNCTION(0x2, "sim"), /* CLK */
98 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
104 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
110 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
133 SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
153 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
[all …]
H A Dpinctrl-sun8i-a23.c4 * Copyright (C) 2014 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include "pinctrl-sunxi.h"
28 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
34 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
40 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
115 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
125 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
130 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
[all …]
H A Dpinctrl-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
13 #include "pinctrl-sunxi.h"
38 SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
78 SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
79 SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */
110 SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
120 SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
130 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
136 SUNXI_FUNCTION(0x4, "spi0")), /* CS */
197 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
[all …]
H A Dpinctrl-sun50i-a64.c4 * Copyright (C) 2016 - ARM Ltd.
7 * Based on pinctrl-sun7i-a20.c, which is:
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
56 SUNXI_FUNCTION(0x5, "sim"), /* CLK */
94 SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
110 SUNXI_FUNCTION(0x4, "spi0")), /* CS */
119 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
180 SUNXI_FUNCTION(0x4, "spi1"), /* CS */
181 SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
[all …]
H A Dpinctrl-sun8i-a83t.c6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
93 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
103 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
108 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
117 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
240 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
280 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960-samsung-expressatt.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
8 model = "Samsung Galaxy Express SGH-I437";
10 chassis-type = "handset";
19 stdout-path = "serial0:115200n8";
33 vmmc-supply = <&pm8921_l5>;
38 vmmc-supply = <&pm8921_l6>;
39 vqmmc-supply = <&pm8921_l7>;
[all …]
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
8 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
15 stdout-path = "serial0:115200n8";
18 ext_l2: gpio-regulator {
19 compatible = "regulator-fixed";
20 regulator-name = "ext_l2";
22 startup-delay-us = <10000>;
23 enable-active-high;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-gta04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on omap3-beagle-xm.dts
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 cpu0-supply = <&vcc>;
27 stdout-path = &uart3;
33 /delete-property/ mmc2;
34 /delete-property/ mmc3;
38 compatible = "regulator-fixed";
39 regulator-name = "ldo_3v3";
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/clk.h>
16 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/spi-davinci.h>
39 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
40 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
106 struct clk *clk; member
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
[all …]
H A Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
12 #include <linux/clk.h>
105 struct clk *clk; member
119 return readl(spi->regs + reg); in mchp_corespi_read()
124 writel(val, spi->regs + reg); in mchp_corespi_write()
141 fifo_max = min(spi->rx_len, FIFO_DEPTH); in mchp_corespi_read_fifo()
146 if (spi->rx_buf) in mchp_corespi_read_fifo()
147 *spi->rx_buf++ = data; in mchp_corespi_read_fifo()
150 spi->rx_len -= i; in mchp_corespi_read_fifo()
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-dove.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
20 #include "pinctrl-mvebu.h"
23 #define INT_REGS_MASK ~(SZ_1M - 1)
68 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); in dove_pmu_mpp_ctrl_get()
86 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); in dove_pmu_mpp_ctrl_set()
90 writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); in dove_pmu_mpp_ctrl_set()
94 writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); in dove_pmu_mpp_ctrl_set()
126 return -EINVAL; in dove_mpp4_ctrl_get()
157 return -EINVAL; in dove_mpp4_ctrl_set()
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
[all …]
/openbmc/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
22 #include <asm/mach-au1x00/au1000.h>
23 #include <asm/mach-au1x00/gpio-au1000.h>
24 #include <asm/mach-au1x00/au1000_dma.h>
25 #include <asm/mach-au1x00/au1100_mmc.h>
26 #include <asm/mach-db1x00/bcsr.h>
51 return -ENODEV; in db1000_board_setup()
57 return -1; in db1500_map_pci_irq()
[all …]

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