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/openbmc/qemu/hw/core/
H A Dresettable.c134 !!rc->phases.enter); in resettable_phase_enter()
135 if (rc->phases.enter) { in resettable_phase_enter()
136 rc->phases.enter(obj, type); in resettable_phase_enter()
160 trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); in resettable_phase_hold()
161 if (rc->phases.hold) { in resettable_phase_hold()
162 rc->phases.hold(obj, type); in resettable_phase_hold()
183 trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); in resettable_phase_exit()
184 if (rc->phases.exit) { in resettable_phase_exit()
185 rc->phases.exit(obj, type); in resettable_phase_exit()
214 * During these phases, the reset subtree being updated is partly in reset in resettable_change_parent()
[all …]
/openbmc/qemu/scripts/coccinelle/
H A Dreset-type.cocci22 // either by directly assigning it to phases.hold or by calling
32 rc->phases.hold = holdfn;
65 rc->phases.exit = exitfn;
104 - rc->phases.phase(obj)@p
105 + rc->phases.phase(obj, RESET_TYPE_COLD)
114 - rc->phases.hold(obj)@p
115 + rc->phases.hold(obj, type)
121 - rc->phases.exit(obj)@p
122 + rc->phases.exit(obj, type)
/openbmc/qemu/include/hw/
H A Dresettable.h63 * for the phases.enter, phases.hold and phases.exit methods, which
79 * @phases.enter: This phase is called when the object enters reset. It
85 * @phases.hold: This phase is called for entry into reset, once every object
86 * in the system which is being reset has had its @phases.enter method called.
89 * @phases.exit: This phase is called when the object leaves the reset state.
120 ResettablePhases phases; member
227 * Save @rc current reset phases into @parent_phases and override @rc phases
230 * override a subset of phases.
/openbmc/linux/drivers/hwmon/pmbus/
H A Dtps53679.c38 #define TPS53681_MFR_SPECIFIC_20 0xe4 /* Number of phases, per page */
83 info->phases[0] = (ret & 0x07) + 1; in tps53679_identify_phases()
180 info->phases[0] = phases_a; in tps53676_identify()
183 info->phases[1] = phases_b; in tps53676_identify()
192 * For reading the total output current (READ_IOUT) for all phases, in tps53681_read_word_data()
194 * FFh to access all phases simultaneously. PHASE may also be set to in tps53681_read_word_data()
197 * current for all phases if the phase is set to 0xff. Instead, it in tps53681_read_word_data()
198 * appears to report the current of one of the phases. Override phase in tps53681_read_word_data()
262 info->phases[0] = 6; in tps53679_probe()
H A Dmp2975.c226 * calculated above and total rail current divided by number phases. in mp2975_read_phase()
232 return max_t(int, DIV_ROUND_CLOSEST(ret, data->info.phases[page]), in mp2975_read_phase()
356 ret = mp2975_data2reg_linear11(ret * info->phases[page] * 1000); in mp2973_read_word_data()
499 for (i = 0 ; i < info->phases[0]; i++) in mp2975_set_phase_rail1()
508 /* Set phases for rail 2 from upper to lower. */ in mp2975_set_phase_rail2()
528 info->phases[0] = ret & GENMASK(3, 0); in mp2975_identify_multiphase()
533 * Rail 1 can be set to $n phases, while rail 2 can be set to less than in mp2975_identify_multiphase()
538 if (info->phases[0] > data->max_phases[0]) in mp2975_identify_multiphase()
543 num_phases2 = min(data->max_phases[0] - info->phases[0], in mp2975_identify_multiphase()
545 if (info->phases[1] && info->phases[1] <= num_phases2) in mp2975_identify_multiphase()
[all …]
H A Ducd9200.c147 * specific commands will apply to all phases of a given page (rail). in ucd9200_probe()
149 * READ_IOUT will return the sum of currents of all phases of a rail, in ucd9200_probe()
151 * for the phases of the rail. in ucd9200_probe()
H A Dmp2856.c272 data->info.phases[0] = (ret > data->max_phases[0]) ? in mp2856_identify_multiphase_rail1()
275 for (i = 0 ; i < data->info.phases[0]; i++) in mp2856_identify_multiphase_rail1()
292 data->info.phases[1] = (ret > data->max_phases[1]) ? in mp2856_identify_multiphase_rail2()
295 for (i = 0 ; i < data->info.phases[0]; i++) in mp2856_identify_multiphase_rail2()
H A Dpmbus.h379 #define PMBUS_PHASES 10 /* Maximum number of phases per page */
406 #define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */
420 u8 phases[PMBUS_PAGES]; /* Number of phases per page */ member
/openbmc/qemu/docs/devel/
H A Dreset.rst116 of an object is split into three well defined phases.
119 startup), all first phases of all objects are executed, then all second phases
120 and then all third phases.
122 The three phases are:
137 count is used to ensure phases are executed only when required. *enter* and
138 *hold* phases are executed only when asserting reset for the first time
159 phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
160 ``phases.exit()``. They all take the object as parameter. The *enter* method
225 In the above example, we override all three phases. It is possible to override
234 phases which does nothing but call the parent class's implementation of the
[all …]
/openbmc/linux/Documentation/driver-api/pm/
H A Ddevices.rst134 they are called in phases for every device, respecting the parent-child
266 System Power Management Phases
269 Suspending or resuming the system is done in several phases. Different phases
274 callbacks. The various phases always run after tasks have been frozen and
275 before they are unfrozen. Furthermore, the ``*_noirq`` phases run at a time
279 All phases use PM domain, bus, type, class or driver callbacks (that is, methods
316 the phases are: ``prepare``, ``suspend``, ``suspend_late``, ``suspend_noirq``.
323 suspend-related phases, during the ``prepare`` phase the device
342 ``suspend_noirq`` phases as well as all of the corresponding phases of
389 "quiesce device" and "save device state" phases, in which cases
[all …]
/openbmc/phosphor-power/phosphor-regulators/docs/config_file/
H A Dlog_phase_fault.md9 A regulator may contain one or more redundant phases:
11 - An "N+2" regulator has two redundant phases
23 | n | Regulator has lost all redundant phases. The regulator is now at redundancy level N. …
H A Dphase_fault_detection.md8 one or more phases that perform the actual voltage regulation.
10 A regulator may have redundant phases. If a redundant phase fails, the regulator
/openbmc/phosphor-power/phosphor-regulators/src/
H A Dphase_fault.hpp29 * controls one or more phases that perform the actual voltage regulation.
31 * A regulator may have redundant phases. If a redundant phase fails, the
41 * Regulator has lost all redundant phases. The regulator is now at
/openbmc/linux/Documentation/hwmon/
H A Dmp2888.rst25 - Programmable Multi-Phase up to 10 Phases.
46 - 'n' is number of configured phases (from 1 to 10);
48 - indexes 2 ... 1 + n for phases.
H A Dpmbus-core.rst178 support multiple phases, the phase parameter can be ignored. If the chip
179 supports multiple phases, a phase value of 0xff indicates all phases.
219 If the chip does not support multiple phases, the phase parameter is
220 ignored. Otherwise, a phase value of 0xff selects all phases.
229 not support multiple phases, the phase parameter is ignored. Otherwise, a phase
230 value of 0xff selects all phases.
H A Dmp2975.rst60 - 'k' is number of configured phases (from 1 to 8);
63 - indexes 2*n+1 ... 2*n + k for phases.
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Drockchip-dw-mshc.yaml72 to control the clock phases, "ciu-sample" is required for tuning
85 low speeds or in case where all phases work at tuning time.
88 rockchip,desired-num-phases:
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Drealtek,otto-wdt.yaml13 The timer has two timeout phases. Both phases have a maximum duration of 32
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c65 /* Make sure we use phases which we can enumerate with */ in dw_mci_rk3288_set_ios()
188 * one since testing bad phases is slow. Skip in dw_mci_rk3288_execute_tuning()
202 dev_warn(host->dev, "All phases bad!"); in dw_mci_rk3288_execute_tuning()
215 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
272 if (of_property_read_u32(np, "rockchip,desired-num-phases", in dw_mci_rk3288_parse_dt()
H A Dsdhci-of-aspeed.c200 const struct mmc_clk_phase *phases, in aspeed_sdhci_phases_to_taps() argument
203 taps->valid = phases->valid; in aspeed_sdhci_phases_to_taps()
205 if (!phases->valid) in aspeed_sdhci_phases_to_taps()
208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); in aspeed_sdhci_phases_to_taps()
209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); in aspeed_sdhci_phases_to_taps()
/openbmc/qemu/hw/sensor/
H A Disl_pmbus_vr.c250 rc->phases.exit = isl_pmbus_vr_exit_reset; in isl69260_class_init()
259 rc->phases.exit = raa228000_exit_reset; in raa228000_class_init()
268 rc->phases.exit = isl_pmbus_vr_exit_reset; in raa229004_class_init()
277 rc->phases.exit = isl69259_exit_reset; in isl69259_class_init()
/openbmc/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9360.yaml42 Capacitance measurement resolution. For both phases, "reference" and
52 PROXRAW filter strength for both phases. A value of 0 represents off,
/openbmc/linux/Documentation/power/
H A Dpci.rst431 management callbacks for this purpose. They are executed in phases such that
433 belonging to the given subsystem before the next phase begins. These phases
440 be preserved, such as one of the ACPI sleep states S1-S3, the phases are:
444 The following PCI bus type's callbacks, respectively, are used in these phases::
509 S1-S3, into the working state (ACPI S0), the phases are:
514 phases::
562 to be free) in the following three phases:
573 The other two phases, however, are different.
591 back to the fully functional state and this is done in the following phases:
617 three phases:
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h41 uint8_t phases; member
68 uint8_t phases; member
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dsc.h161 /* number of phases supported by the polyphase scalers */
181 * num phases x num sets(luma and chroma) x num taps(aligned) x coeff size

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