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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
[all …]
/openbmc/linux/drivers/devfreq/
H A Drk3399_dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
12 #include <linux/devfreq-event.h>
28 #define NS_TO_CYCLE(NS, MHz) (((NS) * (MHz)) / NSEC_PER_USEC) argument
74 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
92 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
95 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target()
99 * Firmware power-domain idling. in rk3399_dmcfreq_target()
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
[all …]
/openbmc/linux/block/
H A Dbfq-iosched.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "blk-cgroup-rwstat.h"
29 * Soft real-time applications are extremely more latency sensitive
30 * than interactive ones. Over-raise the weight of the former to
38 * per-actuator data. The current value is hopefully a good upper
46 * struct bfq_service_tree - per ioprio_class service tree.
48 * Each service tree represents a B-WF2Q+ scheduler on its own. Each
56 /* tree for idle entities (i.e., not backlogged, with V < F_i)*/
57 struct rb_root idle; member
59 /* idle entity with minimum F_i */
[all …]
H A Dblk-throttle.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "blk-cgroup-rwstat.h"
15 #include "blk-stat.h"
16 #include "blk-throttle.h"
31 #define DFL_LATENCY_TARGET (-1L)
50 unsigned long total_latency; /* ns / 1024 */
55 unsigned long latency; /* ns / 1024 */
94 return pd_to_blkg(&tg->pd); in tg_to_blkg()
98 * sq_to_tg - return the throl_grp the specified service queue belongs to
101 * Return the throtl_grp @sq belongs to. If @sq is the top-level one
[all …]
H A Dblk-iolatency.c1 // SPDX-License-Identifier: GPL-2.0
3 * Block rq-qos base io controller
7 * - It's bio based, so the latency covers the whole block layer in addition to
9 * - We will throttle all IO that comes in here if we need to.
10 * - We use the mean latency over the 100ms window. This is because writes can
13 * - By default there's no throttling, we set the queue_depth to UINT_MAX so
44 * number of IO's we're allowed to have in flight. This starts at (u64)-1 down
55 * total_time += min_lat_nsec - actual_io_completion
69 #include <linux/backing-dev.h>
76 #include <linux/blk-mq.h>
[all …]
/openbmc/linux/kernel/sched/
H A Dfair.c1 // SPDX-License-Identifier: GPL-2.0
43 #include <linux/memory-tiers.h>
61 * The initial- and re-scaling of tunables is configurable
65 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
66 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)
67 * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus
74 * Minimal preemption granularity for CPU-bound tasks:
108 return -cpu; in arch_asym_cpu_priority()
129 * Amount of runtime to allocate from global (tg) to local (per-cfs_rq) pool
188 lw->weight += inc; in update_load_add()
[all …]
/openbmc/linux/Documentation/scheduler/
H A Dsched-energy.rst6 ---------------
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
39 --------------------
45 -----------
49 optimization objective to the current performance-only objective for the
50 scheduler. This alternative considers two objectives: energy-efficiency and
54 implications of its decisions rather than blindly applying energy-saving
[all …]
/openbmc/linux/drivers/base/power/
H A Ddomain.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
35 __routine = genpd->dev_ops.callback; \
54 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
60 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
65 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
70 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
81 __acquires(&genpd->slock) in genpd_lock_spin()
85 spin_lock_irqsave(&genpd->slock, flags); in genpd_lock_spin()
86 genpd->lock_flags = flags; in genpd_lock_spin()
[all …]
/openbmc/linux/drivers/dma/
H A Dpl330.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
245 * at 1byte/burst for P<->M and M<->M respectively.
247 * should be enough for P<->M and M<->M respectively.
382 /* Index of the last submitted request or -1 if the DMA is stopped */
423 /* DMA-Engine Channel */
449 /* For D-to-M and M-to-D channels */
453 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-mv64xxx.c182 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | in mv64xxx_i2c_prepare_for_io()
185 if (!drv_data->atomic) in mv64xxx_i2c_prepare_for_io()
186 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN; in mv64xxx_i2c_prepare_for_io()
188 if (msg->flags & I2C_M_RD) in mv64xxx_i2c_prepare_for_io()
191 if (msg->flags & I2C_M_TEN) { in mv64xxx_i2c_prepare_for_io()
192 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; in mv64xxx_i2c_prepare_for_io()
193 drv_data->addr2 = (u32)msg->addr & 0xff; in mv64xxx_i2c_prepare_for_io()
195 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir; in mv64xxx_i2c_prepare_for_io()
196 drv_data->addr2 = 0; in mv64xxx_i2c_prepare_for_io()
212 if (drv_data->offload_enabled) { in mv64xxx_i2c_hw_init()
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c1 // SPDX-License-Identifier: Intel
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
108 * CWL = 5 if tCK >= 2.5ns
109 * 6 if 2.5ns > tCK >= 1.875ns
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
H A Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
H A Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/fsl,imx93-power.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx93-pinfunc.h"
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmc91x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
37 * 29/09/03 Russell King - add driver model support
38 * - ethtool support
39 * - convert to use generic MII interface
40 * - add link up/down notification
41 * - don't try to handle full negotiation in
43 * - clean up (and fix stack overrun) in PHY
112 * Use power-down feature of the chip
197 spin_lock_irqsave(&lp->lock, smc_enable_flags); \
[all …]
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
44 * However, to support simulation-time selection of fast simulation mode, where
47 * check, which is based on the rtl-supplied value, or we dynamically compute
48 * the value to use based on the dynamically-chosen calibration mode
64 * non-skip and skip values
66 * The mask is set to include all bits when not-skipping, but is
70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage()
86 gbl->error_substage = substage; in set_failing_group_stage()
[all …]
/openbmc/linux/tools/power/pm-graph/
H A Dsleepgraph.py2 # SPDX-License-Identifier: GPL-2.0-only
21 # https://01.org/pm-graph
23 # git@github.com:intel/pm-graph
51 # ----------------- LIBRARIES --------------------
73 print('[%09.3f] %s' % (time.time()-mystarttime, msg))
81 # ----------------- CLASSES --------------------
85 # A global, single-instance container used to
107 cgtest = -1
182 tmstart = 'SUSPEND START %Y%m%d-%H:%M:%S.%f'
183 tmend = 'RESUME COMPLETE %Y%m%d-%H:%M:%S.%f'
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath11k/
H A Dmac.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
163 /* new addition in IEEE Std 802.11ax-2021 */
243 #define ath11k_a_rates_size (ARRAY_SIZE(ath11k_legacy_rates) - 4)
407 return -EINVAL; in ath11k_mac_hw_ratecode_to_legacy_rate()
428 for (i = 0; i < sband->n_bitrates; i++) in ath11k_mac_bitrate_to_idx()
429 if (sband->bitrates[i].bitrate == bitrate) in ath11k_mac_bitrate_to_idx()
440 for (nss = IEEE80211_HT_MCS_MASK_LEN - 1; nss >= 0; nss--) in ath11k_mac_max_ht_nss()
452 for (nss = NL80211_VHT_NSS_MAX - 1; nss >= 0; nss--) in ath11k_mac_max_vht_nss()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
[all …]

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