/openbmc/linux/drivers/pci/controller/ |
H A D | pcie-rcar-ep.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe endpoint driver for Renesas R-Car SoCs 6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 13 #include <linux/pci-epc.h> 17 #include "pcie-rcar.h" 21 /* Structure representing the PCIe interface */ 23 struct rcar_pcie pcie; member 33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument 37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init() 40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init() [all …]
|
H A D | pcie-rockchip-ep.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Rockchip AXI PCIe endpoint controller driver 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Simon Xue <xxm@rock-chips.com> 15 #include <linux/pci-epc.h> 17 #include <linux/pci-epf.h> 20 #include "pcie-rockchip.h" 23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver 24 * @rockchip: Rockchip PCIe controller 33 * IRQ) TLP through the PCIe bus. [all …]
|
/openbmc/linux/drivers/pci/controller/cadence/ |
H A D | pcie-cadence-ep.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // Cadence PCIe endpoint controller driver. 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 9 #include <linux/pci-epc.h> 13 #include "pcie-cadence.h" 19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument 27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn() 28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn() 29 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn() 37 struct cdns_pcie_ep *ep = epc_get_drvdata(epc); in cdns_pcie_ep_write_header() local [all …]
|
H A D | pcie-cadence-plat.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Cadence PCIe platform driver. 13 #include "pcie-cadence.h" 18 * struct cdns_plat_pcie - private data for this PCIe platform driver 19 * @pcie: Cadence PCIe controller 20 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex, 24 struct cdns_pcie *pcie; member 34 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument 47 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe() 49 struct cdns_pcie_ep *ep; in cdns_plat_pcie_probe() local [all …]
|
H A D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 10 #include <linux/clk-provider.h> 25 #include "pcie-cadence.h" 27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 80 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument 82 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl() 85 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument 88 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel() [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | fsl,imx6q-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX6 PCIe RC/EP controller 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 14 Generic Freescale i.MX PCIe Root Port and Endpoint controller 22 clock-names: 26 num-lanes: [all …]
|
H A D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 7 which is used to describe the PLL settings at the time of chip-reset. 10 register available in the Freescale PCIe controller register set, 11 which can allow determining the underlying DesignWare PCIe controller version 15 - compatible: should contain the platform identifier such as: 17 "fsl,ls1021a-pcie" 18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" 19 "fsl,ls2088a-pcie" [all …]
|
H A D | ti,j721e-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI J721E PCI EP (PCIe Wrapper) 11 - Kishon Vijay Abraham I <kishon@ti.com> 14 - $ref: cdns-pcie-ep.yaml# 19 - const: ti,j721e-pcie-ep 20 - description: PCIe EP controller in AM64 [all …]
|
H A D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX6 PCIe Endpoint controller 10 - Lucas Stach <l.stach@pengutronix.de> 11 - Richard Zhu <hongxing.zhu@nxp.com> 14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and 15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. 22 - fsl,imx8mm-pcie-ep [all …]
|
H A D | rcar-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ 4 --- 5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas R-Car PCIe Endpoint 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 17 - enum: 18 - renesas,r8a774a1-pcie-ep # RZ/G2M [all …]
|
H A D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm PCIe Endpoint Controller 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 15 - enum: 16 - qcom,sdx55-pcie-ep 17 - qcom,sm8450-pcie-ep 18 - items: [all …]
|
H A D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Socionext UniPhier PCIe endpoint controller 10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare 11 PCI core. It shares common features with the PCIe DesignWare core and 13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml. 16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 21 - socionext,uniphier-pro5-pcie-ep [all …]
|
H A D | ti-pci.txt | 3 PCIe DesignWare Controller 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated) 5 Should be "ti,dra7-pcie-ep" for EP (deprecated) 6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode 7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode 8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode 9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode 10 - phys : list of PHY specifiers (used by generic PHY framework) 11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the 13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", [all …]
|
H A D | cdns,cdns-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Cadence PCIe EP Controller 10 - Tom Joseph <tjoseph@cadence.com> 13 - $ref: cdns-pcie-ep.yaml# 17 const: cdns,cdns-pcie-ep 22 reg-names: 24 - const: reg [all …]
|
H A D | ti,am65-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 14 - $ref: pci-ep.yaml# 19 - ti,am654-pcie-ep 24 reg-names: 26 - const: app [all …]
|
H A D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 11 - reg: base addresses and lengths of the PCIe controller (DBI), 13 - reg-names: Must include the following entries: 14 - "dbi" [all …]
|
H A D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip AXI PCIe Endpoint 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-ep.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie-ep 22 reg-names: [all …]
|
/openbmc/linux/drivers/pci/controller/dwc/ |
H A D | pci-layerscape-ep.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe controller EP driver for Freescale Layerscape SoCs 19 #include "pcie-designware.h" 24 /* PEX PFa PCIE PME and message interrupt registers*/ 35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) 52 static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) in ls_lut_readl() argument 54 struct dw_pcie *pci = pcie->pci; in ls_lut_readl() 56 if (pcie->big_endian) in ls_lut_readl() 57 return ioread32be(pci->dbi_base + offset); in ls_lut_readl() 59 return ioread32(pci->dbi_base + offset); in ls_lut_readl() [all …]
|
H A D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe host controller driver for Samsung Exynos SoCs 5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd. 24 #include "pcie-designware.h" 26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) 28 /* PCIe ELBI registers */ 63 static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) in exynos_pcie_init_clk_resources() argument 65 struct device *dev = ep->pci.dev; in exynos_pcie_init_clk_resources() 68 ret = clk_prepare_enable(ep->clk); in exynos_pcie_init_clk_resources() 70 dev_err(dev, "cannot enable pcie rc clock"); in exynos_pcie_init_clk_resources() [all …]
|
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 3 menu "DesignWare-based PCIe controllers" 18 bool "Amazon Annapurna Labs PCIe controller" 24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe 25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare 27 required only for DT-based platforms. ACPI platforms with the 28 Annapurna Labs PCIe controller don't need to enable this. 31 tristate "Amlogic Meson PCIe controller" 38 and therefore the driver re-uses the DesignWare core functions to 45 bool "Axis ARTPEC-6 PCIe controller (host mode)" [all …]
|
H A D | pcie-keembay.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * PCIe controller driver for Intel Keem Bay 22 #include "pcie-designware.h" 72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument 74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert() 78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument 84 * Specification Revision 1.1, Table-2.4. in keembay_ep_reset_deassert() 88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert() 92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument 96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set() [all …]
|
H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o 3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o 4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o 5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o 6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o 7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o 8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o 9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o 10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o [all …]
|
H A D | pcie-designware.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Synopsys DesignWare PCIe host controller driver 17 #include <linux/dma-mapping.h> 25 #include <linux/pci-epc.h> 26 #include <linux/pci-epf.h> 28 /* DWC PCIe IP-core versions (native support since v4.70a) */ 38 ((_pci)->version _op DW_PCIE_VER_ ## _ver) 52 /* DWC PCIe controller capabilities */ 58 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) 61 set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) [all …]
|
H A D | pcie-designware-plat.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe RC driver for Synopsys DesignWare Core 5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 21 #include "pcie-designware.h" 35 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) in dw_plat_pcie_ep_init() argument 37 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_init() 44 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in dw_plat_pcie_ep_raise_irq() argument 48 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_raise_irq() 52 return dw_pcie_ep_raise_legacy_irq(ep, func_no); in dw_plat_pcie_ep_raise_irq() 54 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); in dw_plat_pcie_ep_raise_irq() [all …]
|
/openbmc/linux/drivers/phy/samsung/ |
H A D | phy-exynos-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Samsung Exynos SoC series PCIe PHY driver 5 * Phy provider for PCIe controller on Exynos SoC series 7 * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd. 34 /* PMU PCIE PHY isolation control */ 37 /* For Exynos pcie phy */ 52 struct exynos_pcie_phy *ep = phy_get_drvdata(phy); in exynos5433_pcie_phy_init() local 54 regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, in exynos5433_pcie_phy_init() 56 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, in exynos5433_pcie_phy_init() 58 regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, in exynos5433_pcie_phy_init() [all …]
|