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/openbmc/openpower-occ-control/
H A Docc_pass_through.hpp8 #include <phosphor-logging/log.hpp>
39 /** @brief Ctor to put pass-through d-bus object on the bus
40 * @param[in] path - Path to attach at
50 /** @brief Pass through command to OCC from dbus
51 * @param[in] command - command to pass-through
56 /** @brief Pass through command to OCC from openpower-occ-control
57 * @param[in] command - command to pass-through
64 * @param[in] mode - desired System Power Mode
65 * @param[in] modeData - data associated some Power Modes
72 /** @brief Pass-through occ path on the bus */
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/openbmc/qemu/docs/system/devices/
H A Dusb-u2f.rst12 QEMU supports both pass-through of a host U2F key device to a VM,
15 ``u2f-passthru``
16 ----------------
18 The ``u2f-passthru`` device allows you to connect a real hardware
20 are passed through to the physical security key connected to the
23 In addition, the dedicated pass-through allows you to share a single
25 simple host device assignment pass-through.
30 .. parsed-literal::
31 |qemu_system| -usb -device u2f-passthru,hidraw=/dev/hidraw0
33 If you don't specify the device, the ``u2f-passthru`` device will
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H A Dusb.rst2 -------------
16 more virtualization-friendly when compared to EHCI and UHCI, thus XHCI
21 |qemu_system| -device qemu-xhci
46 ``-usb`` switch. QEMU will create the UHCI controller as function of
47 the PIIX3 chipset. The USB 1.1 bus will carry the name ``usb-bus.0``.
49 You can use the standard ``-device`` switch to add a EHCI controller to
52 ``-device usb-ehci,id=ehci``. This will give you a USB 2.0 bus named
55 When adding USB devices using the ``-device`` switch you can specify the
58 .. parsed-literal::
60 |qemu_system| -M pc ${otheroptions} \\
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/openbmc/qemu/docs/devel/
H A Dzoned-storage.rst2 zoned-storage
10 https://zonedstorage.io/docs/introduction/zoned-storage
13 -------------------------------------
15 - BLK_Z_HM: The host-managed zoned model only allows sequential writes access
16 to zones. It supports ZBD-specific I/O commands that can be used by a host to
18 - BLK_Z_HA: The host-aware zoned model allows random write operations in
20 - BLK_Z_NONE: The non-zoned model has no zones support. It includes both
21 regular and drive-managed ZBD devices. ZBD-specific I/O commands are not
27 a BlockDriverState graph(for example, raw format on top of file-posix). The
29 the way up to the BlockBackend. If the zoned storage model in file-posix is
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/openbmc/linux/arch/x86/include/uapi/asm/
H A Dsgx.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright(c) 2016-20 Intel Corporation.
12 * enum sgx_page_flags - page control flags
40 * struct sgx_enclave_create - parameter structure for the
49 * struct sgx_enclave_add_pages - parameter structure for the
68 * struct sgx_enclave_init - parameter structure for the
77 * struct sgx_enclave_provision - parameter structure for the
86 * struct sgx_enclave_restrict_permissions - parameters for ioctl
105 * struct sgx_enclave_modify_types - parameters for ioctl
123 * struct sgx_enclave_remove_pages - %SGX_IOC_ENCLAVE_REMOVE_PAGES parameters
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/openbmc/linux/tools/testing/selftests/openat2/
H A Dresolve_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2018-2019 SUSE LLC.
24 * |-- procexe -> /proc/self/exe
25 * |-- procroot -> /proc/self/root
26 * |-- root/
27 * |-- mnt/ [mountpoint]
28 * | |-- self -> ../mnt/
29 * | `-- absself -> /mnt/
30 * |-- etc/
31 * | `-- passwd
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-qmi9 framing from '802.3' to 'raw-ip'.
15 netdev is a headerless p-t-p device in 'raw-ip' mode,
20 through the delegation of the QMI protocol. Userspace
23 firmware is configured for 'raw-ip' mode.
69 Set this to 'Y' to enable 'pass-through' mode, allowing packets
75 'Pass-through' mode can be enabled when the device is in
76 'raw-ip' mode only.
/openbmc/linux/fs/
H A Dattr.c1 // SPDX-License-Identifier: GPL-2.0
6 * changes by Thomas Schoebel-Theuer
25 * setattr_should_drop_sgid - determine whether the setgid bit needs to be
40 umode_t mode = inode->i_mode; in setattr_should_drop_sgid()
53 * setattr_should_drop_suidgid - determine whether the set{g,u}id bit needs to
64 * Return: A mask of ATTR_KILL_S{G,U}ID indicating which - if any - setid bits
70 umode_t mode = inode->i_mode; in setattr_should_drop_suidgid()
87 * chown_ok - verify permissions to chown inode
92 * If the inode has been found through an idmapped mount the idmap of
93 * the vfsmount must be passed through @idmap. This function will then
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/openbmc/phosphor-dbus-interfaces/yaml/org/open_power/OCC/
H A DPassThrough.interface.yaml2 Implement to provide pass-through mechanism to the On Chip Controller (OCC).
4 - name: Send
6 Pass through a command to the OCC.
8 - name: command
19 - name: response
29 - name: SetMode
33 - name: mode
37 - name: frequencyPoint
42 - name: status
/openbmc/linux/drivers/platform/x86/intel/
H A Dcrystal_cove_charger.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for the external-charger IRQ pass-through function of the
7 * pass-through, this requires a separate driver because the PMIC's
38 handle_nested_irq(charger->charger_irq); in crystal_cove_charger_irq()
41 regmap_write(charger->regmap, CHGRIRQ_REG, BIT(0)); in crystal_cove_charger_irq()
50 mutex_lock(&charger->buslock); in crystal_cove_charger_irq_bus_lock()
57 if (charger->mask != charger->new_mask) { in crystal_cove_charger_irq_bus_sync_unlock()
58 regmap_write(charger->regmap, MCHGRIRQ_REG, charger->new_mask); in crystal_cove_charger_irq_bus_sync_unlock()
59 charger->mask = charger->new_mask; in crystal_cove_charger_irq_bus_sync_unlock()
62 mutex_unlock(&charger->buslock); in crystal_cove_charger_irq_bus_sync_unlock()
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/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include "pinctrl-aspeed.h"
18 return pdata->pinmux.ngroups; in aspeed_pinctrl_get_groups_count()
26 return pdata->pinmux.groups[group].name; in aspeed_pinctrl_get_group_name()
35 *pins = &pdata->pinmux.groups[group].pins[0]; in aspeed_pinctrl_get_group_pins()
36 *npins = pdata->pinmux.groups[group].npins; in aspeed_pinctrl_get_group_pins()
44 seq_printf(s, " %s", dev_name(pctldev->dev)); in aspeed_pinctrl_pin_dbg_show()
51 return pdata->pinmux.nfunctions; in aspeed_pinmux_get_fn_count()
59 return pdata->pinmux.functions[function].name; in aspeed_pinmux_get_fn_name()
69 *groups = pdata->pinmux.functions[function].groups; in aspeed_pinmux_get_fn_groups()
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/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_xive.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * pass-through but it's easier to keep around as the same
25 * guest interrupt can alternatively be emulated or pass-through
38 u32 pt_number; /* XIVE Pass-through number if any */
39 struct xive_irq_data *pt_data; /* XIVE Pass-through associated data */
53 bool lsi; /* level-sensitive interrupt */
71 if (state->pt_number) { in kvmppc_xive_select_irq()
73 *out_hw_irq = state->pt_number; in kvmppc_xive_select_irq()
75 *out_xd = state->pt_data; in kvmppc_xive_select_irq()
78 *out_hw_irq = state->ipi_number; in kvmppc_xive_select_irq()
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/openbmc/linux/tools/perf/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 # with a -j option to do parallel builds
6 # If you want to invoke the perf build in some non-standard way then
7 # you can use the 'make -f Makefile.perf' method to invoke it.
11 # Clear out the built-in rules GNU make defines by default (such as .o targets),
12 # so that we pass through all targets to Makefile.perf:
17 # We don't want to pass along options like -j:
23 # in this system: 'make -j8' on a 8-CPU system, etc.
28 …JOBS := $(shell (getconf _NPROCESSORS_ONLN || grep -E -c '^processor|^CPU[0-9]' /proc/cpuinfo) 2>/…
35 # Only pass canonical directory names as the output directory:
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/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/
H A Dapi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
24 #define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
25 #define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
27 #define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
34 #define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
35 #define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
36 #define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
/openbmc/qemu/hw/intc/
H A Drealview_gic.c4 * Copyright (c) 2006-2007 CodeSourcery.
15 #include "hw/qdev-properties.h"
21 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in realview_gic_set_irq()
35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
36 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in realview_gic_realize()
39 busdev = SYS_BUS_DEVICE(&s->gic); in realview_gic_realize()
41 /* Pass through outbound IRQ lines from the GIC */ in realview_gic_realize()
44 /* Pass through inbound GPIO lines to the GIC */ in realview_gic_realize()
45 qdev_init_gpio_in(dev, realview_gic_set_irq, numirq - 32); in realview_gic_realize()
47 memory_region_add_subregion(&s->container, 0, in realview_gic_realize()
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/openbmc/openbmc-test-automation/lib/
H A Dtally_sheet.py15 pass
32 boot_results_fields = collections.OrderedDict([('total', 0), ('pass', 0), ('fail', 0)])
34 boot_results_fields = DotDict([('total', 0), ('pass', 0), ('fail', 0)])
38 boot_test_results.set_sum_fields(['total', 'pass', 'fail'])
40 boot_test_results.set_calc_fields(['total=pass+fail'])
47 boot_test_results.inc_row_field('BMC Power On', 'pass')
48 boot_test_results.inc_row_field('BMC Power Off', 'pass')
57 Boot Type Total Pass Fail
58 ----------------------------------- ----- ---- ----
123 calc_fields A string expression such as 'total=pass+fail'
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/openbmc/linux/arch/arm/boot/bootp/
H A Dinit.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2000-2003 Russell King.
7 * "Header" file for splitting kernel + initrd. Note that we pass
8 * r0 through to r3 straight through.
20 _start: add lr, pc, #-0x8 @ lr = current load addr
22 ldmia r13!, {r4-r6} @ r5 = dest, r6 = length
27 * Setup the initrd parameters to pass to the kernel. This can only be
30 ldmia r13, {r5-r9} @ get size and addr of initrd
63 move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time
64 stmia r5!, {r7 - r10}
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/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Daltera-freeze-bridge.txt5 changes from passing through the bridge. The controller can also
6 unfreeze/enable the bridges which allows traffic to pass through the
10 - compatible : Should contain "altr,freeze-bridge-controller"
11 - regs : base address and size for freeze bridge module
13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
16 freeze-controller@100000450 {
17 compatible = "altr,freeze-bridge-controller";
19 bridge-enable = <0>;
H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
15 which prevents signal changes from passing through the bridge. The controller
16 can also couple / enable the bridges which allows traffic to pass through the
19 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
20 eXchange AXI shutdown manager prevents AXI traffic from passing through the
21 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
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/openbmc/qemu/include/sysemu/
H A Dreset.h4 * Copyright (c) 2003-2008 Fabrice Bellard
31 #include "qapi/qapi-events-run-state.h"
41 * they were added, using the three-phase Resettable protocol,
42 * so first all objects go through the enter phase, then all objects
43 * go through the hold phase, and then finally all go through the
68 * @opaque: opaque data to pass to @func
75 * of the 3-phase reset.
91 * @opaque: opaque data to pass to @func
116 * This function performs the low-level work needed to do a complete reset
/openbmc/bmcweb/
H A DOEM_SCHEMAS.md17 Because of that, OEM properties in an open-source project pose many problems
21 possible. Adding machine-specific resources, properties, and types defeats a
22 large amount of reuse, as clients must implement machine-specific APIs, some of
25 and therefore needs to take care when adding new, non-standard APIs, given the
29 quality and testing than their spec-driven alternatives, given the lack of
60 2. Present the new feature and use case to DMTF either through the
62 possible, message the new feature through the normal openbmc communications
75 maintainers, and they will walk you through how to develop the feature under
80 resources, should pass the redfish service validator, should pass the csdl
82 the same level of quality as non-OEM.
/openbmc/linux/Documentation/i2c/muxes/
H A Di2c-mux-gpio.rst2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
11 from a master I2C bus and a hardware MUX controlled through GPIO pins.
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
22 | | | |---------------| |
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/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst1 Hyper-V Enlightenments
6 -----------
11 It may, however, be hard-to-impossible to add support for these interfaces to
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
20 -----
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
23 QEMU, individual enlightenments can be enabled through CPU flags, e.g:
25 .. parsed-literal::
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/openbmc/linux/include/linux/regulator/
H A Dmax8973-regulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * max8973-regulator.h -- MAXIM 8973 regulator
5 * Interface for regulator driver for MAXIM 8973 DC-DC step-down
18 * Client need to pass this information with ORed
38 * struct max8973_regulator_platform_data - max8973 regulator platform data.
47 * @enable_ext_control: Enable the voltage enable/disable through external
49 * voltage output will be enabled/disabled through EN bit of
51 * @enable_gpio: Enable GPIO. If EN pin is controlled through GPIO from host
53 * it should be -1.
54 * @dvs_gpio: GPIO for dvs. It should be -1 if this is tied with fixed logic.
/openbmc/linux/scripts/gcc-plugins/
H A Dstackleak_plugin.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2017 by the PaX Team <pageexec@freemail.hu>
13 * - after alloca();
14 * - for the functions with a stack frame size greater than or equal
15 * to the "track-min-size" plugin parameter.
22 * - use fprintf() to stderr, debug_generic_expr(), debug_gimple_stmt(),
24 * - add "-fdump-tree-all -fdump-rtl-all" to the plugin CFLAGS in
25 * Makefile.gcc-plugins to see the verbose dumps of the gcc passes;
26 * - use gcc -E to understand the preprocessing shenanigans;
27 * - use gcc with enabled CFG/GIMPLE/SSA verification (--enable-checking).
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