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/openbmc/u-boot/board/corscience/tricorder/
H A Dtricorder.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include "tricorder-eeprom.h"
33 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); in board_init()
39 * get_eeprom - read the eeprom
41 * @eeprom - pointer to a eeprom struct to fill
43 * This function will panic() on wrong EEPROM content
45 static void get_eeprom(struct tricorder_eeprom *eeprom) in get_eeprom() argument
49 if (!eeprom) in get_eeprom()
50 panic("No eeprom given!\n"); in get_eeprom()
67 /* BMS is _not_ set, do the EEPROM check */ in get_eeprom()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dvia-velocity.txt4 - compatible : Should be "via,velocity-vt6110"
5 - reg : Address and length of the io space
6 - interrupts : Should contain the controller interrupt line
9 - no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
10 devices quite often set this data in uboot and do not provide an eeprom.
11 Specify this option if you have no external eeprom.
16 compatible = "via,velocity-vt6110";
19 no-eeprom;
H A Ddavicom,dm9000.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
18 - description: Address registers
19 - description: Data registers
24 davicom,no-eeprom:
26 description: Configuration EEPROM is not available
28 davicom,ext-phy:
32 reset-gpios:
[all …]
/openbmc/openbmc/meta-ampere/meta-jade/recipes-ampere/platform/ampere-utils/
H A Dampere_firmware_upgrade.sh5 FRU_DEVICE="/sys/bus/i2c/devices/3-0050/eeprom"
7 if ! command -v ampere_fru_upgrade;
9 echo "Bypass fru update as no ampere_fru_upgrade available"
12 ampere_fru_upgrade -d $FRU_DEVICE -f "$IMAGE"
21 if ! command -v ampere_eeprom_prog;
23 echo "Bypass SCP firmware update as no ampere_eeprom_prog available"
28 chassisstate=$(obmcutil chassisstate | awk -F. '{print $NF}')
37 while [ "$cnt" -gt 0 ];
39 cnt=$((cnt - 1))
42 chassisstate_off=$(obmcutil chassisstate | awk -F. '{print $NF}')
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-eeprom-read.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
17 * EEPROM access time values:
19 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
[all …]
/openbmc/u-boot/cmd/
H A Deeprom.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Support for read and write access to EEPROM like memory devices. This
9 * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
10 * FRAM devices read and write data at bus speed. In particular, there is no
11 * write delay. Also, there is no limit imposed on the number of bytes that can
14 * Use the following configuration options to ensure no unneeded performance
15 * degradation (typical for EEPROM) is incured for FRAM memory:
25 #include <eeprom.h>
46 #define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
49 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
[all …]
/openbmc/linux/drivers/nvmem/
H A Drave-sp-eeprom.c1 // SPDX-License-Identifier: GPL-2.0+
4 * EEPROM driver for RAVE SP
10 #include <linux/mfd/rave-sp.h>
12 #include <linux/nvmem-provider.h>
18 * enum rave_sp_eeprom_access_type - Supported types of EEPROM access
20 * @RAVE_SP_EEPROM_WRITE: EEPROM write
21 * @RAVE_SP_EEPROM_READ: EEPROM read
29 * enum rave_sp_eeprom_header_size - EEPROM command header sizes
31 * @RAVE_SP_EEPROM_HEADER_SMALL: EEPROM header size for "small" devices (< 8K)
32 * @RAVE_SP_EEPROM_HEADER_BIG: EEPROM header size for "big" devices (> 8K)
[all …]
/openbmc/linux/drivers/misc/eeprom/
H A Didt_89hpesx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
5 * IDT PCIe-switch NTB Linux driver
8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
12 * This driver primarily is developed to have an access to EEPROM device of
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
14 * operations from/to EEPROM, which is located at private (so called Master)
16 * binary sysfs-file in the device directory:
17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
[all …]
/openbmc/u-boot/drivers/net/
H A De1000_spi.c6 /*-----------------------------------------------------------------------
18 * This may be interrupted with Ctrl-C if "intr" is true, otherwise it will
31 /* Pre-read the control register */ in e1000_spi_xfer()
38 return -1; in e1000_spi_xfer()
69 din[i >> 3] &= ~((mask << 1) - 1); in e1000_spi_xfer()
86 printf("ERROR: No such e1000 device: e1000#%u\n", bus); in spi_setup_slave()
91 if (hw->eeprom.type != e1000_eeprom_spi) { in spi_setup_slave()
92 E1000_ERR(hw, "No attached SPI EEPROM found!\n"); in spi_setup_slave()
98 E1000_ERR(hw, "No such SPI chip: %u\n", cs); in spi_setup_slave()
102 E1000_ERR(hw, "Only SPI MODE-0 is supported!\n"); in spi_setup_slave()
[all …]
/openbmc/entity-manager/docs/
H A Daddress_size_detection_modes.md1 # EEPROM address size detection modes
4 address byte(s) needed for a given EEPROM device.
6 ## MODE-1
8 The existing upstream function isDevice16Bit() bases on sending 1-byte write
9 operation (with a STOP condition) and 8 subsequent 1-byte read operations with
12 ### This MODE-1 expects the following logic
14 - If the device requires 1 address byte, it EXPECTS that the data will be read
16 - If the device requires 2 address bytes, it EXPECTS that the data will be read
20 ### Issue and potential issue with this MODE-1
22 - If any "2 address bytes" EEPROM from any vendor has the same data in all
[all …]
/openbmc/u-boot/board/phytec/phycore_rk3288/
H A Dphycore-rk3288.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <eeprom.h>
20 unsigned char *e = p + sizeof(struct rk3288_som) - 1; in valid_rk3288_som()
28 return hw == som->bs; in valid_rk3288_som()
38 /* Get the identificatioin page of M24C32-D EEPROM */ in rk_board_late_init()
39 off = fdt_path_offset(gd->fdt_blob, "eeprom0"); in rk_board_late_init()
41 printf("%s: No eeprom0 path offset\n", __func__); in rk_board_late_init()
47 printf("%s: Could not find EEPROM\n", __func__); in rk_board_late_init()
58 printf("%s: Could not read EEPROM\n", __func__); in rk_board_late_init()
63 printf("Invalid data or wrong EEPROM layout version.\n"); in rk_board_late_init()
[all …]
/openbmc/linux/Documentation/misc-devices/
H A Deeprom.rst2 Kernel driver eeprom
7 * Any EEPROM chip in the designated address range
9 Prefix: 'eeprom'
11 Addresses scanned: I2C 0x50 - 0x57
28 24C01 1K 0x50 (shadows at 0x51 - 0x57)
29 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs)
30 24C02 2K 0x50 - 0x57
35 24C16 16K 0x50 (additional data at 0x51 - 0x57)
38 Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
39 Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dplx9052.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Definitions for the PLX-9052 PCI interface chip
7 * COMEDI - Linux Control and Measurement Device Interface
15 * INTCSR - Interrupt Control/Status register
33 * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and
55 #define PLX9052_CNTRL_PCI_R_NO_FLUSH BIT(16) /* read no flush mode */
56 #define PLX9052_CNTRL_PCI_R_NO_WRITE BIT(17) /* read no write mode */
60 #define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */
61 #define PLX9052_CNTRL_EEPROM_CLK BIT(24) /* EEPROM clock */
62 #define PLX9052_CNTRL_EEPROM_CS BIT(25) /* EEPROM chip select */
[all …]
/openbmc/phosphor-fan-presence/docs/presence/
H A Deeprom.md1 # eeprom chapter
5 Some fans have EEPROMs on them. In these cases, the `eeprom` JSON stanza can be
6 used to have the application re-bind the EEPROM driver to the EEPROM instance
7 after a new fan is detected. This will trigger the EEPROM to be read by the
14 - ["bus_address"](#bus_address)
15 - ["driver_name"](#driver_name)
16 - ["bind_delay_ms"](#bind_delay_ms)
20 The I2C bus and address string of the form BB-AAAA that is used by the I2C
24 "bus_address": "3-0050"
29 The name of the eeprom driver in sysfs.
[all …]
/openbmc/linux/include/media/
H A Dtveeprom.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * tveeprom - Contains structures and functions to work with Hauppauge
11 * enum tveeprom_audio_processor - Specifies the type of audio processor
14 * @TVEEPROM_AUDPROC_NONE: No audio processor present
28 * struct tveeprom - Contains the fields parsed from Hauppauge eeproms
38 * @has_MAC_address: 0: no MAC, 1: MAC present, 2: unknown.
94 * tveeprom_hauppauge_analog - Fill struct tveeprom using the contents
95 * of the eeprom previously filled at
98 * @tvee: Struct to where the eeprom parsed data will be filled;
101 * eeprom read from the Hauppauge device.
[all …]
/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Deeprom.c2 drivers/net/ethernet/dec/tulip/eeprom.c
5 Written/copyright 1994-2001 by Donald Becker.
20 /* Serial EEPROM section. */
27 /* Known cards that have old-style EEPROMs. */
33 0x0004, 0x009E, /* 10baseT-FD */
35 0x0905, 0x006D, /* 100baseTx-FD */ }},
38 0x0108, 0x8021, /* 100baseFx-FD */
40 0x0104, 0x009E, /* 10baseT-FD */
42 0x0105, 0x006D, /* 100baseTx-FD */ }},
43 {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
[all …]
/openbmc/linux/drivers/media/usb/em28xx/
H A Dem28xx-i2c.c1 // SPDX-License-Identifier: GPL-2.0+
3 // em28xx-i2c.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
20 #include <media/v4l2-common.h>
23 /* ----------------------------------------------------------- */
35 dev_printk(KERN_DEBUG, &dev->intf->dev, \
54 switch (dev->i2c_speed & 0x03) { in em28xx_i2c_timeout()
80 return -EOPNOTSUPP; in em2800_i2c_send_bytes()
82 b2[5] = 0x80 + len - 1; in em2800_i2c_send_bytes()
93 ret = dev->em28xx_write_regs(dev, 4 - len, &b2[4 - len], 2 + len); in em2800_i2c_send_bytes()
95 dev_warn(&dev->intf->dev, in em2800_i2c_send_bytes()
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dmisc.c1 // SPDX-License-Identifier: GPL-2.0+
24 /* dram_init must store complete ramsize in gd->ram_size */ in dram_init()
25 gd->ram_size = get_ram_size( in dram_init()
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
34 gd->bd->bi_dram[0].size = gd->ram_size; in dram_init_banksize()
42 * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
60 printf("Read from EEPROM @ 0x%02x failed\n", in dvevm_read_mac_address()
76 val = readl(&davinci_syscfg_regs->cfgchip3); in davinci_emac_mii_mode_sel()
81 writel(val, &davinci_syscfg_regs->cfgchip3); in davinci_emac_mii_mode_sel()
85 * If there is no MAC address in the environment, then it will be initialized
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-zii-spb4.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * SPB - Seat Power Box
11 /dts-v1/;
19 stdout-path = &uart0;
27 gpio-leds {
28 compatible = "gpio-leds";
29 pinctrl-0 = <&pinctrl_leds_debug>;
30 pinctrl-names = "default";
32 led-debug {
35 linux,default-trigger = "heartbeat";
[all …]
H A Dvf610-zii-ssmb-spu3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * SSMB - SPU3 Switch Management Board
7 * SPU - Seat Power Unit
11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
15 /dts-v1/;
23 stdout-path = &uart0;
31 gpio-leds {
32 compatible = "gpio-leds";
33 pinctrl-0 = <&pinctrl_leds_debug>;
34 pinctrl-names = "default";
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_eeprom.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 /* AT24CM02 and M24M02-R have a 256-byte write page size.
31 #define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
35 /* EEPROM memory addresses are 19-bits long, which can
37 * The upper 3 bits are sent as part of the 7-bit
38 * "Device Type Identifier"--an I2C concept, which for EEPROM devices
39 * is hard-coded as 1010b, indicating that it is an EEPROM
40 * device--this is the wire format, followed by the upper
41 * 3 bits of the 19-bit address, followed by the direction,
42 * followed by two bytes holding the rest of the 16-bits of
[all …]
/openbmc/u-boot/board/freescale/mpc8349itx/
H A DREADME1 Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
2 ---------------------------------------------------
6 The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
7 the Freescale MPC8349E processor in a Mini-ITX form factor.
9 The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
11 A) One 8MB on-board flash EEPROM chip, instead of two.
12 B) No SATA controller
13 C) No Compact Flash slot
14 D) No Mini-PCI slot
15 E) No Vitesse 7385 5-port Ethernet switch
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ibm-bonnell.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/leds/leds-pca955x.h>
12 compatible = "ibm,bonnell-bmc", "aspeed,ast2600";
23 stdout-path = &uart5;
32 reserved-memory {
33 #address-cells = <1>;
[all …]
/openbmc/u-boot/board/kosagi/novena/
H A Dnovena.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <eeprom.h>
15 #include <asm/arch/imx-regs.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/sata.h>
23 #include <asm/mach-imx/video.h>
90 return -1; in drv_keyboard_init()
114 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-zii-rmu2.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * RMU - Remote Modem Unit
10 /dts-v1/;
11 #include <dt-bindings/thermal/thermal.h>
16 compatible = "zii,imx7d-rmu2", "fsl,imx7d";
19 stdout-path = &uart2;
22 gpio-leds {
23 compatible = "gpio-leds";
24 pinctrl-0 = <&pinctrl_leds_debug>;
25 pinctrl-names = "default";
[all …]

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