| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | marvell,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.h | 8 unsigned int tCH; /* Enable signal hold time */
9 unsigned int tCS; /* Enable signal setup time */
23 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
31 * When you want to use this feature, you should not enable the
33 * attached with different nand chip. The different page size
41 * Controller and the Data Flash Controller, the arbiter
52 /* use an flash-based bad block table */
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| H A D | pxa3xx_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/mtd/nand/raw/pxa3xx_nand.c
12 #include <nand.h>
123 writel((val), (info)->mmio_base + (off))
126 readl((info)->mmio_base + (off))
131 ERR_DMABUSERR = -1,
132 ERR_SENDCMD = -2,
133 ERR_UNCORERR = -3,
134 ERR_BBERR = -4,
135 ERR_CORERR = -5,
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| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-385-atl-x530.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
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| /openbmc/linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 This option allows to enable specific memory controller drivers,
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
86 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-385-atl-x530.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
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| H A D | armada-375-db.dts | 3 * (DB-88F6720)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
49 /dts-v1/;
50 #include <dt-bindings/gpio/gpio.h>
51 #include "armada-375.dtsi"
55 compatible = "marvell,a375-db", "marvell,armada375";
58 stdout-path = "serial0:115200n8";
62 /* So that mvebu u-boot can update the MAC addresses */
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| H A D | armada-385-amc.dts | 3 * (DB-88F6820-AMC)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
43 #include "armada-385.dtsi"
44 #include <dt-bindings/gpio/gpio.h>
48 compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
51 stdout-path = "serial0:115200n8";
70 internal-regs {
72 clock-frequency = <100000>;
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| H A D | armada-xp-maxbcm.dts | 4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
64 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
67 stdout-path = "serial0:115200n8";
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| H A D | armada-xp-gp.dts | 3 * (DB-MV784MP-GP)
5 * Copyright (C) 2013-2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is dual-licensed: you can use it either under the terms
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
64 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
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| H A D | armada-cp110-master.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
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| /openbmc/linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
29 Say y here to enable support for the ARM Logic Module bus
33 tristate "Broadcom STB GISB bus arbiter"
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
38 arbiter. This driver provides timeout and target abort error handling
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
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| /openbmc/u-boot/include/configs/ |
| H A D | MPC8308RDB.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
24 * On-board devices
107 * Arbiter Setup
109 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
110 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
128 * consist of two chips HY5PS12621BFP-C4 from HYNIX
201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
243 * NAND Flash on the Local Bus
270 | BR_PS_8 /* 8-bit port */ \
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| H A D | mpc8308_p1m.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
19 * On-board devices
110 * Arbiter Setup
112 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
113 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
131 * consist of two chips HY5PS12621BFP-C4 from HYNIX
205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
305 * Addresses are mapped 1-1.
317 /* enable PCIE clock */
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| H A D | MPC8313ERDB.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
23 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
55 * On-board devices
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
152 /* 0x129048c6 */ /* P9-45,may need tuning */
169 /* set burst length to 8 for 32-bit data path */
220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
239 /* drivers/mtd/nand/raw/nand.c */
362 * Addresses are mapped 1-1.
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| /openbmc/u-boot/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
41 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask); in reset_cpu()
42 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst); in reset_cpu()
148 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ in get_sar_freq()
150 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ in get_sar_freq()
184 *sar_freq = sar_freq_tab[i - 1]; in get_sar_freq()
197 puts("MV78230-"); in print_cpuinfo()
200 puts("MV78260-"); in print_cpuinfo()
203 puts("MV78460-"); in print_cpuinfo()
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
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| /openbmc/linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-ipq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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| /openbmc/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
135 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
138 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
300 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
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