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/openbmc/linux/drivers/mtd/nand/
H A Dbbt.c1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
16 * nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
17 * @nand: NAND device
19 * Initialize the in-memory BBT.
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
28 nand->bbt.cache = bitmap_zalloc(nblocks * bits_per_block, GFP_KERNEL); in nanddev_bbt_init()
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/openbmc/u-boot/drivers/mtd/nand/
H A Dbbt.c1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
18 * nanddev_bbt_init() - Initialize the BBT (Bad Block Table)
19 * @nand: NAND device
21 * Initialize the in-memory BBT.
25 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
28 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
32 nand->bbt.cache = kzalloc(nwords, GFP_KERNEL); in nanddev_bbt_init()
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/openbmc/u-boot/include/linux/mtd/
H A Dspinand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
16 #include <linux/mtd/nand.h>
18 #include <linux/spi/spi-mem.h>
22 #include <spi-mem.h>
23 #include <linux/mtd/nand.h>
27 * Standard SPI NAND flash operations
121 * Standard SPI NAND flash commands
152 * struct spinand_id - SPI NAND id structure
157 * struct_spinand_id->data contains all bytes returned after a READ_ID command,
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H A Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
16 * struct nand_memory_organization - Memory organization structure
17 * @bits_per_cell: number of bits per NAND cell
24 * @ntargets: total number of targets exposed by the NAND device
50 * struct nand_row_converter - Information needed to convert an absolute offset
62 * struct nand_pos - NAND position object
63 * @target: the NAND target/die
69 * These information are usually used by specific sub-layers to select the
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/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
10 L2 cache
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
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/openbmc/linux/include/linux/mtd/
H A Dspinand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
197 * struct spinand_id - SPI NAND id structure
214 * struct spinand_devid - SPI NAND device id structure
222 * read_id opcode + 1-byte address.
233 * struct manufacurer_ops - SPI NAND manufacturer specific operations
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H A Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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H A Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
97 * Enable generic NAND 'page erased' check. This check is only done when
98 * ecc.correct() returns -EBADMSG.
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/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
18 cache
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
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H A Dflctl-nand.txt1 FLCTL NAND controller
4 - compatible : "renesas,shmobile-flctl-sh7372"
5 - reg : Address range of the FLCTL
6 - interrupts : flste IRQ number
7 - nand-bus-width : bus width to NAND chip
10 - dmas: DMA specifier(s)
11 - dma-names: name for each DMA specifier. Valid names are
17 The device tree may optionally contain sub-nodes describing partitions of the
23 #address-cells = <1>;
24 #size-cells = <1>;
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/openbmc/u-boot/doc/
H A DREADME.nand-boot-ppc4401 -----------------------------
2 NAND boot on PPC440 platforms
3 -----------------------------
5 This document describes the U-Boot NAND boot feature as it
8 The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
9 completely without NOR FLASH. This can be done by using the NAND
10 boot feature of the 440 NAND flash controller (NDFC).
15 ------------------------------------------------------
16 Will load first 4k from NAND (SPL) into cache and execute it from there.
19 ---------------------------------
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H A DREADME.m54418twr4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m54418twr/m54418twr.c Dram setup
13 - board/freescale/m54418twr/Makefile Makefile
14 - board/freescale/m54418twr/config.mk config make
15 - board/freescale/m54418twr/u-boot.lds Linker description
16 - board/freescale/m54418twr/sbf_dram_init.S
19 - arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
20 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
21 - arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
22 - arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dmisc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
33 { "nand", "NAND Flash (1.8V)", },
34 { "nand", "NAND Flash (3.0V)", },
44 return -EINVAL; in dram_init()
62 /* Disable the L2 cache */ in v7_outer_cache_enable()
63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
65 writel(0x0, &pl310->pl310_tag_latency_ctrl); in v7_outer_cache_enable()
66 writel(0x10, &pl310->pl310_data_latency_ctrl); in v7_outer_cache_enable()
69 setbits_le32(&pl310->pl310_aux_ctrl, in v7_outer_cache_enable()
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/openbmc/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
74 possible to tune the L2 cache performance up by setting the data,
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
86 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
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/openbmc/u-boot/drivers/mtd/nand/spi/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
21 #include <linux/spi/spi-mem.h>
26 #include <spi-mem.h>
30 /* SPI NAND index visible in MTD names */
37 struct nand_device *nand = spinand_to_nand(spinand); in spinand_cache_op_adjust_colum() local
40 if (nand->memorg.planes_per_lun < 2) in spinand_cache_op_adjust_colum()
44 shift = fls(nand->memorg.pagesize); in spinand_cache_op_adjust_colum()
45 *column |= req->pos.plane << shift; in spinand_cache_op_adjust_colum()
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/openbmc/u-boot/board/freescale/m5373evb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m5373evb/m5373evb.c Dram setup
13 - board/freescale/m5373evb/mii.c Mii access
14 - board/freescale/m5373evb/Makefile Makefile
15 - board/freescale/m5373evb/config.mk config make
16 - board/freescale/m5373evb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf532x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
20 - arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dfsl_elbc_spl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
5 * (C) Copyright 2006-2008
15 #include <nand.h>
24 uint32_t status = in_be32(&regs->ltesr); in nand_wait()
53 if (offs & (block_size - 1)) { in nand_spl_load_image()
60 out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | in nand_spl_load_image()
62 out_be32(&regs->fir, in nand_spl_load_image()
69 out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); in nand_spl_load_image()
70 out_be32(&regs->fir, in nand_spl_load_image()
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/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
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/openbmc/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbcma_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
51 /* Offset into the NAND block and deal with the flash cache separately */ in brcmnand_bcma_read_reg()
57 val = bcma_cc_read32(sc->cc, offset); in brcmnand_bcma_read_reg()
70 /* Offset into the NAND block */ in brcmnand_bcma_write_reg()
80 bcma_cc_write32(sc->cc, offset, val); in brcmnand_bcma_write_reg()
93 /* Reset the cache address to ensure we are already accessing the in brcmnand_bcma_prepare_data_bus()
94 * beginning of a sub-page. in brcmnand_bcma_prepare_data_bus()
96 bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0); in brcmnand_bcma_prepare_data_bus()
101 struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev); in brcmnand_bcma_nand_probe()
104 soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL); in brcmnand_bcma_nand_probe()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-98dx3236.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
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