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Searched +full:mux +full:- +full:reg +full:- +full:masks (Results 1 – 25 of 75) sorted by relevance

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/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
11 #include "clk-uniphier.h"
16 unsigned int reg; member
17 const unsigned int *masks; member
25 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_set_parent() local
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
28 mux->vals[index]); in uniphier_clk_mux_set_parent()
33 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw); in uniphier_clk_mux_get_parent() local
39 ret = regmap_read(mux->regmap, mux->reg, &val); in uniphier_clk_mux_get_parent()
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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
22 reg: true
24 '#mux-control-cells':
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/openbmc/linux/drivers/mux/
H A Dmmio.c1 // SPDX-License-Identifier: GPL-2.0
3 * MMIO register bitfield-controlled multiplexer driver
12 #include <linux/mux/driver.h>
18 static int mux_mmio_set(struct mux_control *mux, int state) in mux_mmio_set() argument
20 struct regmap_field **fields = mux_chip_priv(mux->chip); in mux_mmio_set()
22 return regmap_field_write(fields[mux_control_get_index(mux)], state); in mux_mmio_set()
30 { .compatible = "mmio-mux", },
31 { .compatible = "reg-mux", },
38 struct device *dev = &pdev->dev; in mux_mmio_probe()
39 struct device_node *np = dev->of_node; in mux_mmio_probe()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx-iomuxc-gpr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
19 - items:
20 - const: fsl,imx8mq-iomuxc-gpr
21 - const: syscon
22 - const: simple-mfd
23 - items:
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/openbmc/linux/sound/ppc/
H A Dawacs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 unsigned byteswap; /* Data is little-endian if 1 */
29 /* Audio Bit Masks */
32 /* Audio Control Reg Bit Masks */
33 /* ----- ------- --- --- ----- */
43 /* Audio Codec Control Reg Bit Masks */
44 /* ----- ----- ------- --- --- ----- */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
47 #define MASK_EXMODEADDR (0x3ff << 12) /* Extended Mode Address -- 10 bits */
48 #define MASK_EXMODEDATA (0xfff) /* Extended Mode Data -- 12 bits */
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/openbmc/linux/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,npcm-gcr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
21 - enum:
22 - nuvoton,wpcm450-gcr
23 - nuvoton,npcm750-gcr
24 - nuvoton,npcm845-gcr
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/openbmc/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017 Socionext Inc.
8 #include <clk-uclass.h>
14 #include "clk-uniphier.h"
17 * struct uniphier_clk_priv - private data for UniPhier clock driver
33 val = readl(priv->base + gate->reg); in uniphier_clk_gate_enable()
34 val |= BIT(gate->bit); in uniphier_clk_gate_enable()
35 writel(val, priv->base + gate->reg); in uniphier_clk_gate_enable()
39 const struct uniphier_clk_mux_data *mux, in uniphier_clk_mux_set_parent() argument
45 for (i = 0; i < mux->num_parents; i++) { in uniphier_clk_mux_set_parent()
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H A Dclk-uniphier.h1 /* SPDX-License-Identifier: GPL-2.0+ */
28 u16 reg; member
35 u16 reg; member
36 u32 masks[UNIPHIER_CLK_MUX_MAX_PARENTS]; member
46 struct uniphier_clk_mux_data mux; member
65 .reg = (_reg), \
H A Dclk-uniphier-mio.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include "clk-uniphier.h"
23 .data.mux = { \
35 .reg = 0x30 + 0x200 * (ch), \
36 .masks = { \
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
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H A Dpalmas.txt3 The TI palmas family current members :-
12 - compatible : Should be from the list
23 - interrupt-controller : palmas has its own internal IRQs
24 - #interrupt-cells : should be set to 2 for IRQ number and flags
26 The second cell is the flags, encoded as the trigger masks from
27 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
30 ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
37 reg = <0x48>
38 interrupt-parent = <&intc>;
39 interrupt-controller;
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
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H A Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
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H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
37 reg = <0x0 0x80000000 0x1 0x00000000>;
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
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/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730-gbs.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
10 compatible = "quanta,gbs-bmc","nuvoton,npcm730";
71 stdout-path = &serial0;
75 reg = <0 0x40000000>;
78 gpio-keys {
79 compatible = "gpio-keys";
80 sas-cable0 {
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H A Dnuvoton-npcm730-kudo.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
41 stdout-path = &serial3;
45 reg = <0 0x40000000>;
48 iio-hwmon {
49 compatible = "iio-hwmon";
50 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
55 compatible = "nuvoton,npcm750-jtag-master";
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/openbmc/linux/drivers/hwmon/
H A Dads7871.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ads7871 - driver for TI ADS7871 A/D converter
22 #define REG_GAIN_MUX 4 /*Gain/Mux Register*/
34 /*Instruction Bit masks*/
40 /*bit masks for Rev/Oscillator Control Register*/
44 #define MUX_G_BV 4 /*allows for reg = (gain << MUX_G_BV) | ...*/
47 /*bit masks for Rev/Oscillator Control Register*/
59 #include <linux/hwmon-sysfs.h>
69 static int ads7871_read_reg8(struct spi_device *spi, int reg) in ads7871_read_reg8() argument
72 reg = reg | INST_READ_BM; in ads7871_read_reg8()
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
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H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
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/openbmc/u-boot/arch/arm/dts/
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
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H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c33 #define REG(reg)\ macro
34 mpc30->mpc_regs->reg
37 mpc30->base.ctx
41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
92 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
97 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
98 MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode, in mpc3_set_out_rate_control()
99 MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1); in mpc3_set_out_rate_control()
155 /* Wait for memory to be powered on - we won't be able to write to it otherwise. */ in mpc3_power_on_ogam_lut()
175 struct dcn3_xfer_func_reg *reg) in mpc3_ogam_get_reg_field() argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_generic.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
40 generic->shifts->field_name, generic->masks->field_name
43 generic->base.base.ctx
44 #define REG(reg)\ macro
45 (generic->regs->reg)
52 dal_hw_gpio_destruct(&pin->base); in dal_hw_generic_destruct()
76 REG_UPDATE_2(mux, in set_config()
77 GENERIC_EN, config_data->config.generic_mux.enable_output_from_mux, in set_config()
78 GENERIC_SEL, config_data->config.generic_mux.mux_select); in set_config()
99 dal_hw_gpio_construct(&pin->base, id, en, ctx); in dal_hw_generic_construct()
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/openbmc/linux/sound/soc/codecs/
H A Dcs35l36.c1 // SPDX-License-Identifier: GPL-2.0
3 // cs35l36.c -- CS35L36 ALSA SoC audio driver
27 #include <sound/soc-dapm.h>
247 static bool cs35l36_readable_reg(struct device *dev, unsigned int reg) in cs35l36_readable_reg() argument
249 switch (reg) { in cs35l36_readable_reg()
389 if (reg >= CS35L36_PAC_PMEM_WORD0 && in cs35l36_readable_reg()
390 reg <= CS35L36_PAC_PMEM_WORD1023) in cs35l36_readable_reg()
397 static bool cs35l36_precious_reg(struct device *dev, unsigned int reg) in cs35l36_precious_reg() argument
399 switch (reg) { in cs35l36_precious_reg()
409 static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg) in cs35l36_volatile_reg() argument
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