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/openbmc/linux/drivers/mux/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 mux-core-objs := core.o
7 mux-adg792a-objs := adg792a.o
8 mux-adgs1408-objs := adgs1408.o
9 mux-gpio-objs := gpio.o
10 mux-mmio-objs := mmio.o
12 obj-$(CONFIG_MULTIPLEXER) += mux-core.o
13 obj-$(CONFIG_MUX_ADG792A) += mux-adg792a.o
14 obj-$(CONFIG_MUX_ADGS1408) += mux-adgs1408.o
15 obj-$(CONFIG_MUX_GPIO) += mux-gpio.o
[all …]
H A Dmmio.c1 // SPDX-License-Identifier: GPL-2.0
3 * MMIO register bitfield-controlled multiplexer driver
12 #include <linux/mux/driver.h>
18 static int mux_mmio_set(struct mux_control *mux, int state) in mux_mmio_set() argument
20 struct regmap_field **fields = mux_chip_priv(mux->chip); in mux_mmio_set()
22 return regmap_field_write(fields[mux_control_get_index(mux)], state); in mux_mmio_set()
30 { .compatible = "mmio-mux", },
31 { .compatible = "reg-mux", },
38 struct device *dev = &pdev->dev; in mux_mmio_probe()
39 struct device_node *np = dev->of_node; in mux_mmio_probe()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
22 be called mux-adg792a.
32 be called mux-adgs1408.
35 tristate "GPIO-controlled Multiplexer"
38 GPIO-controlled Multiplexer controller.
46 be called mux-gpio.
49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
59 be called mux-mmio.
/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
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/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 * struct imx_pin_mmio - MMIO pin configurations
23 * @mux_mode: the mux mode for this pin.
37 * struct imx_pin_scu - SCU pin configurations
38 * @mux: the mux mode for this pin.
47 * struct imx_pin - describes a single i.MX pin
49 * @conf: config type of this pin, either mmio or scu
54 struct imx_pin_mmio mmio; member
60 * struct imx_pin_reg - describe a pin reg map
61 * @mux_reg: mux register offset
[all …]
H A Dpinctrl-imx.c1 // SPDX-License-Identifier: GPL-2.0+
30 #include "pinctrl-imx.h"
43 for (i = 0; i < pctldev->num_groups; i++) { in imx_pinctrl_find_group_by_name()
45 if (grp && !strcmp(grp->name, name)) in imx_pinctrl_find_group_by_name()
55 seq_printf(s, "%s", dev_name(pctldev->dev)); in imx_pin_dbg_show()
63 const struct imx_pinctrl_soc_info *info = ipctl->info; in imx_dt_node_to_map()
75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); in imx_dt_node_to_map()
77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); in imx_dt_node_to_map()
78 return -EINVAL; in imx_dt_node_to_map()
81 if (info->flags & IMX_USE_SCU) { in imx_dt_node_to_map()
[all …]
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
20 return chnl->ctype == IPC_CTYPE_WWAN && in ipc_imem_check_wwan_ips()
21 chnl->if_id == IPC_MEM_MUX_IP_CH_IF_ID; in ipc_imem_check_wwan_ips()
32 ipc_imem->device_sleep = state; in ipc_imem_msg_send_device_sleep()
34 return ipc_protocol_tq_msg_send(ipc_imem->ipc_protocol, in ipc_imem_msg_send_device_sleep()
42 if (pipe->nr_of_queued_entries >= pipe->max_nr_of_queued_entries) in ipc_imem_dl_skb_alloc()
45 return ipc_protocol_dl_td_prepare(ipc_imem->ipc_protocol, pipe); in ipc_imem_dl_skb_alloc()
59 struct ipc_pipe *pipe = &ipc_imem->channels[i].dl_pipe; in ipc_imem_tq_td_alloc_timer()
61 if (!pipe->is_open || pipe->nr_of_queued_entries > 0) in ipc_imem_tq_td_alloc_timer()
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H A Diosm_ipc_imem_ops.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
18 dev_dbg(ipc_imem->dev, "%s if id: %d", in ipc_imem_sys_wwan_open()
19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
25 return -EIO; in ipc_imem_sys_wwan_open()
28 return ipc_mux_open_session(ipc_imem->mux, if_id); in ipc_imem_sys_wwan_open()
35 if (ipc_imem->mux && if_id >= IP_MUX_SESSION_START && in ipc_imem_sys_wwan_close()
37 ipc_mux_close_session(ipc_imem->mux, if_id); in ipc_imem_sys_wwan_close()
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H A Diosm_ipc_mmio.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
29 IPC_MEM_DEVICE_IPC_INVALID = -1
52 /* mmio scratchpad info */
68 * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
69 * @base: Base address of MMIO region
75 * @mux_protocol: mux protocol
94 * ipc_mmio_init - Allocate mmio instance data
95 * @mmio_addr: Mapped AP base address of the MMIO area.
98 * Returns: address of mmio instance data or NULL if fails.
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H A Diosm_ipc_imem.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
70 #define IMEM_IRQ_DONT_CARE (-1)
88 * Modem crash notification configuration. If this value is non-zero then
91 * will use out-of-band method to notify about it's Crash.
100 #define IPC_CB(skb) ((struct ipc_skb_cb *)((skb)->cb))
144 * enum ipc_ctype - Enum defining supported channel type needed for control
175 * struct ipc_pipe - Structure for Pipe.
221 * struct ipc_mem_channel - Structure for Channel.
251 * enum ipc_phase - Different AP and CP phases.
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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx-iomuxc-gpr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
19 - items:
20 - const: fsl,imx8mq-iomuxc-gpr
21 - const: syscon
22 - const: simple-mfd
23 - items:
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
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/openbmc/linux/drivers/ata/
H A Dahci_xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene SoC SATA Host Controller Driver
22 #define DRV_NAME "xgene-ahci"
27 /* MUX CSR */
88 void __iomem *csr_mux; /* MUX CSR address of IP */
93 dev_dbg(ctx->dev, "Release memory from shutdown\n"); in xgene_ahci_init_memram()
94 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); in xgene_ahci_init_memram()
95 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ in xgene_ahci_init_memram()
97 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { in xgene_ahci_init_memram()
98 dev_err(ctx->dev, "failed to release memory from shutdown\n"); in xgene_ahci_init_memram()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,npcm-gcr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
21 - enum:
22 - nuvoton,wpcm450-gcr
23 - nuvoton,npcm750-gcr
24 - nuvoton,npcm845-gcr
[all …]
/openbmc/linux/drivers/mfd/
H A Dstm32-lptimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer parent driver.
6 * Inspired by Benjamin Gaignard's stm32-timers driver
9 #include <linux/mfd/stm32-lptimer.h>
31 * Low-Power Timer supports it. in stm32_lptimer_detect_encoder()
33 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
38 ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val); in stm32_lptimer_detect_encoder()
42 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
47 ddata->has_encoder = !!(val & STM32_LPTIM_ENC); in stm32_lptimer_detect_encoder()
54 struct device *dev = &pdev->dev; in stm32_lptimer_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,am654-hbmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
14 const: ti,am654-hbmc
19 power-domains: true
20 '#address-cells': true
21 '#size-cells': true
24 mux-controls:
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/openbmc/linux/drivers/spi/
H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
17 #include <linux/mux/consumer.h>
24 #include <linux/spi/spi-mem.h>
27 #include "spi-dw.h"
35 struct mux_control *mux; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
[all …]
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
24 #define TYPE_STM32L4X5_RCC "stm32l4x5-rcc"
27 /* In the Stm32l4x5 clock tree, mux have at most 7 sources */
38 /* NB: Prescaler are assimilated to mux with one source and one output */
72 * Mux that have only one input and one output assigned to as peripheral.
76 /* - AHB1 */
[all …]
H A Dxlnx-versal-pmc-iou-slcr.h34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
40 * + sysbus MMIO region 0: MemoryRegion for the device's registers
44 * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
46 * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
48 * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
50 * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
/openbmc/qemu/include/hw/ssi/
H A Dxlnx-versal-ospi.h34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module
41 * + sysbus MMIO region 0: MemoryRegion for the device's registers
42 * + sysbus MMIO region 1: MemoryRegion for flash memory linear address space
45 * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
47 * + Property "dac-with-indac": Allow both direct accesses and indirect
49 * + Property "indac-write-disabled": Disable indirect access writes.
60 #define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
38 wakeup-source;
45 wakeup-source;
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730-gbs.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
10 compatible = "quanta,gbs-bmc","nuvoton,npcm730";
71 stdout-path = &serial0;
78 gpio-keys {
79 compatible = "gpio-keys";
80 sas-cable0 {
81 label = "sas-cable0";
[all …]
/openbmc/linux/arch/arm/mach-vt8500/
H A Dvt8500.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-vt8500/vt8500.c
12 #include <asm/mach-types.h>
40 /* SoC MMIO registers */
70 fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb"); in vt8500_init()
72 np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio"); in vt8500_init()
92 pr_err("%s: Could not remap GPIO mux\n", __func__); in vt8500_init()
99 fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb"); in vt8500_init()
101 np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio"); in vt8500_init()
104 "wm,wm8650-gpio"); in vt8500_init()
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