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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-camss.yaml228 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
233 clocks = <&mmcc CAMSS_AHB_CLK>,
234 <&mmcc CAMSS_CPHY_CSID0_CLK>,
235 <&mmcc CAMSS_CPHY_CSID1_CLK>,
236 <&mmcc CAMSS_CPHY_CSID2_CLK>,
237 <&mmcc CAMSS_CPHY_CSID3_CLK>,
238 <&mmcc CAMSS_CSI0_AHB_CLK>,
239 <&mmcc CAMSS_CSI0_CLK>,
240 <&mmcc CAMSS_CPHY_CSID0_CLK>,
241 <&mmcc CAMSS_CSI0PIX_CLK>,
[all …]
H A Dqcom,msm8996-camss.yaml222 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
227 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
228 <&mmcc CAMSS_ISPIF_AHB_CLK>,
229 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
230 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
231 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
232 <&mmcc CAMSS_CSI0_AHB_CLK>,
233 <&mmcc CAMSS_CSI0_CLK>,
234 <&mmcc CAMSS_CSI0PHY_CLK>,
235 <&mmcc CAMSS_CSI0PIX_CLK>,
[all …]
H A Dqcom,msm8996-venus.yaml108 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
114 clocks = <&mmcc VIDEO_CORE_CLK>,
115 <&mmcc VIDEO_AHB_CLK>,
116 <&mmcc VIDEO_AXI_CLK>,
117 <&mmcc VIDEO_MAXI_CLK>;
119 power-domains = <&mmcc VENUS_GDSC>;
144 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
146 power-domains = <&mmcc VENUS_CORE0_GDSC>;
151 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
153 power-domains = <&mmcc VENUS_CORE1_GDSC>;
H A Dqcom,sdm660-venus.yaml108 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
114 clocks = <&mmcc VIDEO_CORE_CLK>,
115 <&mmcc VIDEO_AHB_CLK>,
116 <&mmcc VIDEO_AXI_CLK>,
117 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
144 power-domains = <&mmcc VENUS_GDSC>;
148 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
150 power-domains = <&mmcc VENUS_CORE0_GDSC>;
155 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
157 power-domains = <&mmcc VENUS_CORE0_GDSC>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,mmcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
25 - qcom,mmcc-msm8974
26 - qcom,mmcc-msm8992
27 - qcom,mmcc-msm8994
28 - qcom,mmcc-msm8996
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,msm8998-mdss.yaml66 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
76 clocks = <&mmcc MDSS_AHB_CLK>,
77 <&mmcc MDSS_AXI_CLK>,
78 <&mmcc MDSS_MDP_CLK>;
89 power-domains = <&mmcc MDSS_GDSC>;
100 clocks = <&mmcc MDSS_AHB_CLK>,
101 <&mmcc MDSS_AXI_CLK>,
102 <&mmcc MNOC_AHB_CLK>,
103 <&mmcc MDSS_MDP_CLK>,
104 <&mmcc MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,msm8998-dpu.yaml59 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
70 clocks = <&mmcc MDSS_AHB_CLK>,
71 <&mmcc MDSS_AXI_CLK>,
72 <&mmcc MNOC_AHB_CLK>,
73 <&mmcc MDSS_MDP_CLK>,
74 <&mmcc MDSS_VSYNC_CLK>;
H A Dmdp4.yaml88 <&mmcc 77>,
89 <&mmcc 86>,
90 <&mmcc 102>,
91 <&mmcc 75>,
92 <&mmcc 97>,
93 <&mmcc 12>;
H A Dhdmi.yaml183 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
199 clocks = <&mmcc MDSS_MDP_CLK>,
200 <&mmcc MDSS_AHB_CLK>,
201 <&mmcc MDSS_HDMI_CLK>,
202 <&mmcc MDSS_HDMI_AHB_CLK>,
203 <&mmcc MDSS_EXTPCLK_CLK>;
H A Dgpu.yaml225 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
237 clocks = <&mmcc OXILI_GFX3D_CLK>,
238 <&mmcc OXILICX_AHB_CLK>,
239 <&mmcc OXILICX_AXI_CLK>;
245 power-domains = <&mmcc OXILICX_GDSC>;
259 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm660.dtsi171 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
172 <&mmcc PCLK1_CLK_SRC>;
176 clocks = <&mmcc MDSS_MDP_CLK>,
177 <&mmcc MDSS_BYTE1_CLK>,
178 <&mmcc MDSS_BYTE1_INTF_CLK>,
179 <&mmcc MNOC_AHB_CLK>,
180 <&mmcc MDSS_AHB_CLK>,
181 <&mmcc MDSS_AXI_CLK>,
182 <&mmcc MISC_AHB_CLK>,
183 <&mmcc MDSS_PCLK1_CLK>,
[all …]
H A Dsdm630.dtsi9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
711 <&mmcc AHB_CLK_SRC>;
1451 mmcc: clock-controller@c8c0000 { label
1452 compatible = "qcom,mmcc-sdm630";
1485 power-domains = <&mmcc MDSS_GDSC>;
1487 clocks = <&mmcc MDSS_AHB_CLK>,
1488 <&mmcc MDSS_AXI_CLK>,
1489 <&mmcc MDSS_VSYNC_CLK>,
1490 <&mmcc MDSS_MDP_CLK>;
1514 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
[all …]
H A Dmsm8996.dtsi8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
921 <&mmcc AHB_CLK_SRC>;
949 mmcc: clock-controller@8c0000 { label
950 compatible = "qcom,mmcc-msm8996";
971 assigned-clocks = <&mmcc MMPLL9_PLL>,
972 <&mmcc MMPLL1_PLL>,
973 <&mmcc MMPLL3_PLL>,
974 <&mmcc MMPLL4_PLL>,
975 <&mmcc MMPLL5_PLL>;
993 power-domains = <&mmcc MDSS_GDSC>;
[all …]
H A Dmsm8996pro-xiaomi-scorpio.dts36 clocks = <&mmcc MDSS_MDP_CLK>,
37 <&mmcc MMSS_MMAGIC_AHB_CLK>,
38 <&mmcc MDSS_AHB_CLK>,
39 <&mmcc MDSS_AXI_CLK>,
40 <&mmcc MMSS_MISC_AHB_CLK>,
41 <&mmcc MDSS_BYTE0_CLK>,
42 <&mmcc MDSS_PCLK0_CLK>,
43 <&mmcc MDSS_ESC0_CLK>,
44 <&mmcc SMMU_MDP_AHB_CLK>,
45 <&mmcc SMMU_MDP_AXI_CLK>;
[all …]
H A Dmsm8992-xiaomi-libra.dts49 clocks = <&mmcc MDSS_AHB_CLK>,
50 <&mmcc MDSS_AXI_CLK>,
51 <&mmcc MDSS_VSYNC_CLK>,
52 <&mmcc MDSS_MDP_CLK>,
53 <&mmcc MDSS_BYTE0_CLK>,
54 <&mmcc MDSS_PCLK0_CLK>,
55 <&mmcc MDSS_ESC0_CLK>;
56 power-domains = <&mmcc MDSS_GDSC>;
H A Dmsm8998-oneplus-common.dtsi39 clocks = <&mmcc MDSS_AHB_CLK>,
40 <&mmcc MDSS_AXI_CLK>,
41 <&mmcc MDSS_VSYNC_CLK>,
42 <&mmcc MDSS_MDP_CLK>,
43 <&mmcc MDSS_BYTE0_CLK>,
44 <&mmcc MDSS_BYTE0_INTF_CLK>,
45 <&mmcc MDSS_PCLK0_CLK>,
46 <&mmcc MDSS_ESC0_CLK>;
47 power-domains = <&mmcc MDSS_GDSC>;
H A Dmsm8998.dtsi7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
2732 mmcc: clock-controller@c8c0000 { label
2733 compatible = "qcom,mmcc-msm8998";
2770 clocks = <&mmcc MDSS_AHB_CLK>,
2771 <&mmcc MDSS_AXI_CLK>,
2772 <&mmcc MDSS_MDP_CLK>;
2777 power-domains = <&mmcc MDSS_GDSC>;
2800 clocks = <&mmcc MDSS_AHB_CLK>,
2801 <&mmcc MDSS_AXI_CLK>,
2802 <&mmcc MNOC_AHB_CLK>,
[all …]
H A Dmsm8992.dtsi18 &mmcc {
19 compatible = "qcom,mmcc-msm8992";
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
846 mmcc: clock-controller@4000000 { label
847 compatible = "qcom,mmcc-apq8064";
1180 <&mmcc GFX3D_CLK>,
1181 <&mmcc GFX3D_AHB_CLK>,
1182 <&mmcc GFX3D_AXI_CLK>,
1183 <&mmcc MMSS_IMEM_AHB_CLK>;
1280 clocks = <&mmcc DSI_M_AHB_CLK>,
1281 <&mmcc DSI_S_AHB_CLK>,
1282 <&mmcc AMP_AHB_CLK>,
[all …]
H A Dqcom-msm8226.dtsi10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
322 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
323 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
324 <&mmcc CAMSS_CCI_CCI_CLK>;
395 mmcc: clock-controller@fd8c0000 { label
396 compatible = "qcom,mmcc-msm8226";
823 power-domains = <&mmcc MDSS_GDSC>;
825 clocks = <&mmcc MDSS_AHB_CLK>,
826 <&mmcc MDSS_AXI_CLK>,
827 <&mmcc MDSS_VSYNC_CLK>;
[all …]
H A Dqcom-msm8974.dtsi7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
1113 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1114 <&mmcc MMSS_S0_AXI_CLK>;
1829 mmcc: clock-controller@fd8c0000 { label
1830 compatible = "qcom,mmcc-msm8974";
1866 power-domains = <&mmcc MDSS_GDSC>;
1868 clocks = <&mmcc MDSS_AHB_CLK>,
1869 <&mmcc MDSS_AXI_CLK>,
1870 <&mmcc MDSS_VSYNC_CLK>;
1892 clocks = <&mmcc MDSS_AHB_CLK>,
[all …]
/openbmc/linux/drivers/clk/qcom/
H A DMakefile22 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
50 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
51 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
52 obj-$(CONFIG_MSM_MMCC_8994) += mmcc-msm8994.o
53 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
54 obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o
93 obj-$(CONFIG_SDM_MMCC_660) += mmcc-sdm660.o
/openbmc/linux/sound/soc/codecs/
H A Dcs42l73.c33 u8 spc, mmcc, spfs; member
785 u8 mmcc; member
940 u8 spc, mmcc; in cs42l73_set_dai_fmt() local
943 mmcc = snd_soc_component_read(component, CS42L73_MMCC(id)); in cs42l73_set_dai_fmt()
947 mmcc |= CS42L73_MS_MASTER; in cs42l73_set_dai_fmt()
951 mmcc &= ~CS42L73_MS_MASTER; in cs42l73_set_dai_fmt()
967 if (mmcc & CS42L73_MS_MASTER) { in cs42l73_set_dai_fmt()
1003 priv->config[id].mmcc = mmcc; in cs42l73_set_dai_fmt()
1055 if (priv->config[id].mmcc & CS42L73_MS_MASTER) { in cs42l73_pcm_hw_params()
1065 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", in cs42l73_pcm_hw_params()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dmsm,iommu-v0.txt50 <&mmcc SMMU_AHB_CLK>,
51 <&mmcc MDP_AXI_CLK>;
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml101 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
112 <&mmcc OCMEMCX_OCMEMNOC_CLK>;

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