| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
18 one CPU local timer instantiated in MCT for every CPU in the system.
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| H A D | marvell,armada-370-xp-timer.txt | 1 Marvell Armada 370 and Armada XP Timers
2 ---------------------------------------
5 - compatible: Should be one of the following
6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
10 then local timer interrupts
11 - reg: Should contain location and length for timers register. First
13 local/private timers.
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| /openbmc/linux/Documentation/timers/ |
| H A D | highres.rst | 2 High resolution timers and dynamic ticks design notes
8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
34 the base implementation are covered in Documentation/timers/hrtimers.rst. See
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| H A D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
12 architecture-specific overrides of the sched_clock() function and some
13 delay timers.
17 on this timeline, providing facilities such as high-resolution timers.
18 sched_clock() is used for scheduling and timestamping, and delay timers
23 -------------
31 n bits which count from 0 to (2^n)-1 and then wraps around to 0 and start over.
36 shall be as stable and correct as possible as compared to a real-world wall
46 When the wall-clock accuracy of the clock source isn't satisfactory, there
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| /openbmc/linux/Documentation/virt/hyperv/ |
| H A D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Clocks and Timers
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
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| /openbmc/linux/kernel/ |
| H A D | cpu_pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
53 * cpu_pm_register_notifier - register a driver with cpu_pm
74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm
94 * cpu_pm_enter - CPU low power entry notifier
102 * co-processor, interrupt controller and its PM extensions, local CPU
103 * timers context save/restore which shouldn't be interrupted. Hence it
115 * cpu_pm_exit - CPU low power exit notifier
120 * Notified drivers can include VFP co-processor, interrupt controller
121 * and its PM extensions, local CPU timers context save/restore which
133 * cpu_cluster_pm_enter - CPU cluster low power entry notifier
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| /openbmc/linux/net/mac80211/ |
| H A D | pm.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020-2021 Intel Corporation
11 #include "driver-ops.h"
14 static void ieee80211_sched_scan_cancel(struct ieee80211_local *local) in ieee80211_sched_scan_cancel() argument
16 if (ieee80211_request_sched_scan_stop(local)) in ieee80211_sched_scan_cancel()
18 cfg80211_sched_scan_stopped_locked(local->hw.wiphy, 0); in ieee80211_sched_scan_cancel()
23 struct ieee80211_local *local = hw_to_local(hw); in __ieee80211_suspend() local
27 if (!local->open_count) in __ieee80211_suspend()
30 local->suspending = true; in __ieee80211_suspend()
33 ieee80211_scan_cancel(local); in __ieee80211_suspend()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | bcm_kona_timer.c | 1 // SPDX-License-Identifier: GPL-2.0
32 static struct kona_bcm_timers timers; variable
37 * We use the peripheral timers for system tick, the cpu global timer for
65 * Read 64-bit free running counter in kona_timer_get_counter()
66 * 1. Read hi-word in kona_timer_get_counter()
67 * 2. Read low-word in kona_timer_get_counter()
68 * 3. Read hi-word again in kona_timer_get_counter()
70 * if new hi-word is not equal to previously read hi-word, then in kona_timer_get_counter()
73 * if new hi-word is equal to previously read hi-word then stop. in kona_timer_get_counter()
81 } while (--loop_limit); in kona_timer_get_counter()
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| H A D | exynos_mct.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7 * Exynos4 MCT(Multi-Core Timer) support
63 /* There are four Global timers starting with 0 offset */
65 /* Local timers count starts after global timer count */
69 /* Max number of local timers */
70 #define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ)
87 * local timer interrupts grow over two digits
167 * exynos4_read_count_64 - Read all 64-bits of the global counter
169 * This will read all 64-bits of the global counter taking care to make sure
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| H A D | arm_arch_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
133 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write()
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); in arch_timer_reg_write()
149 writel_relaxed((u32)val, timer->base + CNTV_CTL); in arch_timer_reg_write()
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| H A D | arc_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
26 #include <soc/arc/timers.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
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| H A D | timer-fttmr010.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
46 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
62 * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
63 * The aspeed timers move bits around in the control register and lacks
78 * timers.
79 * The registers don't exist and they are not needed on aspeed timers
81 * - aspeed timer overflow interrupt is controlled by bits in Control
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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| /openbmc/qemu/hw/timer/ |
| H A D | exynos4210_mct.c | 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
26 * Consists of two timers. First represents Free Running Counter and second
31 * | <-------------------------------------------------------------- |
32 * | --------------------------------------------frc---------------> |
37 * | -------------> |
46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
121 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10)
122 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
145 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2011 Freescale Semiconductor, Inc.
24 * Local Access Window
27 u32 bar; /* LBIU local access window base address register */
28 u32 ar; /* LBIU local access window attribute register */
39 law83xx_t lblaw[4]; /* LBIU local access window */
41 law83xx_t pcilaw[2]; /* PCI local access window */
43 law83xx_t pcielaw[2]; /* PCI Express local access window */
45 law83xx_t ddrlaw[2]; /* DDR local access window */
143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
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| /openbmc/linux/include/linux/usb/ |
| H A D | otg-fsm.h | 1 // SPDX-License-Identifier: GPL-2.0+
18 * Table:6-4
23 * Table:6-5
29 /* Standard OTG timers */
38 /* Auxiliary timers */
49 * struct otg_fsm - OTG state machine according to the OTG spec
54 * @id: TRUE for B-device, FALSE for A-device.
56 * ADP measurement taken at n-2, differs by more than CADP_THR
60 * A-Device state inputs
61 * @a_srp_det: TRUE if the A-device detects SRP
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | i8253.c | 1 // SPDX-License-Identifier: GPL-2.0
18 * the two timers is used
28 * requires to know the local APIC timer frequency as it normally is
56 * - On SMP PIT does not scale due to i8253_lock in init_pit_clocksource()
57 * - when HPET is enabled in init_pit_clocksource()
58 * - when local APIC timer is active (PIT is switched off) in init_pit_clocksource()
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| /openbmc/linux/Documentation/virt/kvm/x86/ |
| H A D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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| /openbmc/qemu/docs/system/i386/ |
| H A D | hyperv.rst | 1 Hyper-V Enlightenments
6 -----------
11 It may, however, be hard-to-impossible to add support for these interfaces to
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
20 -----
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
25 .. parsed-literal::
27 |qemu_system| --enable-kvm --cpu host,hv_relaxed,hv_vpindex,hv_time, ...
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| /openbmc/linux/kernel/time/ |
| H A D | hrtimer.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
4 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
5 * Copyright(C) 2006-2007 Timesys Corp., Thomas Gleixner
7 * High-resolution kernel timers
9 * In contrast to the low-resolution timeout API, aka timer wheel,
50 #include "tick-internal.h"
53 * Masks for selecting the soft and hard context timers from
54 * cpu_base->active
57 #define HRTIMER_ACTIVE_HARD ((1U << MASK_SHIFT) - 1)
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| /openbmc/linux/net/llc/ |
| H A D | llc_conn.c | 2 * llc_conn.c - Driver routines for connection component.
5 * 2001-2003 by Arnaldo Carvalho de Melo <acme@conectiva.com.br>
51 * llc_conn_state_process - sends event to connection state machine
65 struct llc_sock *llc = llc_sk(skb->sk); in llc_conn_state_process()
68 ev->ind_prim = ev->cfm_prim = 0; in llc_conn_state_process()
72 rc = llc_conn_service(skb->sk, skb); in llc_conn_state_process()
78 switch (ev->ind_prim) { in llc_conn_state_process()
94 * skb->sk pointing to the newly created struct sock in in llc_conn_state_process()
95 * llc_conn_handler. -acme in llc_conn_state_process()
98 skb_queue_tail(&sk->sk_receive_queue, skb); in llc_conn_state_process()
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| /openbmc/linux/include/net/sctp/ |
| H A D | command.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1999-2001 Cisco, Motorola
12 * lksctp developers <linux-sctp@vger.kernel.org>
55 SCTP_CMD_COOKIEECHO_RESTART, /* High level, do cookie-echo timer work. */
59 SCTP_CMD_HB_TIMERS_START, /* Start the heartbeat timers. */
60 SCTP_CMD_HB_TIMER_UPDATE, /* Update a heartbeat timers. */
61 SCTP_CMD_HB_TIMERS_STOP, /* Stop the heartbeat timers. */
73 SCTP_CMD_SETUP_T2, /* Hi-level, setup T2-shutdown parms. */
82 SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
83 SCTP_CMD_T3_RTX_TIMERS_STOP, /* Stops T3-rtx pending timers */
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| /openbmc/linux/Documentation/process/ |
| H A D | maintainer-tip.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------------
11 aggregation tree for several sub-maintainer trees. The tip tree gitweb URL
16 - **x86 architecture**
22 x86-specific KVM and XEN patches.
30 mail alias which distributes mails to the x86 top-level maintainer
32 ``linux-kernel@vger.kernel.org``, otherwise your mail ends up only in
35 - **Scheduler**
37 Scheduler development takes place in the -tip tree, in the
38 sched/core branch - with occasional sub-topic trees for
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| /openbmc/qemu/include/hw/ppc/ |
| H A D | openpic.h | 41 /* Timers don't exist but this makes the code happy... */
50 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
75 bool level:1; /* level-triggered */
92 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
122 /* Count of IRQ sources asserting on non-INT outputs */
150 /* Sub-regions */
161 /* Local registers per output pin */
165 OpenPICTimer timers[OPENPIC_MAX_TMR]; member
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| /openbmc/u-boot/include/configs/ |
| H A D | ti_omap3_common.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
32 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
49 * OMAP3 has 12 GP timers, they can be driven by the system clock
51 * This rate is divided by a local divisor.
|