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/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64v_4core_virtio.dts1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
5 /dts-v1/;
7 compatible = "loongson,loongson64v-4core-virtio";
8 #address-cells = <2>;
9 #size-cells = <2>;
11 cpuintc: interrupt-controller {
12 #address-cells = <0>;
13 #interrupt-cells = <1>;
14 interrupt-controller;
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H A Dloongson64g-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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H A Dloongson64c-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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H A Dloongson64c_8core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-8core-rs780e";
13 htpic: interrupt-controller@1efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
H A Dloongson64c_4core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-rs780e";
13 htpic: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
H A Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K1000 chip, as the primary package interrupt controller which
18 - $ref: /schemas/interrupt-controller.yaml#
23 - loongson,liointc-1.0
24 - loongson,liointc-1.0a
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H A Dloongson,htvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips for
18 const: loongson,htvec-1.0
21 maxItems: 1
24 minItems: 1
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H A Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
21 const: loongson,htpic-1.0
24 maxItems: 1
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/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
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/openbmc/linux/drivers/irqchip/
H A Dirq-loongson-liointc.c1 // SPDX-License-Identifier: GPL-2.0
36 * LIOINTC_REG_INTC_POL register is only valid for Loongson-2K series, and
37 * Loongson-3 series behave as noops.
73 struct irq_chip_generic *gc = handler->priv->gc; in liointc_chained_handle_irq()
79 pending = readl(handler->priv->core_isr[core]); in liointc_chained_handle_irq()
83 if (handler->priv->has_lpc_irq_errata && in liointc_chained_handle_irq()
84 (handler->parent_int_map & gc->mask_cache & in liointc_chained_handle_irq()
94 generic_handle_domain_irq(gc->domain, bit); in liointc_chained_handle_irq()
106 writel(readl(gc->reg_base + offset) | mask, in liointc_set_bit()
107 gc->reg_base + offset); in liointc_set_bit()
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/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
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/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c2 * Generic Loongson-3 Platform support
4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
32 #include "hw/char/serial-mm.h"
45 #include "hw/pci-host/gpex.h"
52 #include "qemu/error-report.h"
59 * Loongson-3's virtual machine BIOS can be obtained here:
60 * 1, https://github.com/loongson-community/firmware-nonfree
66 #define RTC_IRQ 1
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/openbmc/linux/
H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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