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/openbmc/linux/drivers/gpio/
H A Dgpio-aggregator.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2019-2020 Glider bv
7 #define DRV_NAME "gpio-aggregator"
45 static int aggr_add_gpio(struct gpio_aggregator *aggr, const char *key, in aggr_add_gpio()
46 int hwnum, unsigned int *n) in aggr_add_gpio()
50 lookups = krealloc(aggr->lookups, struct_size(lookups, table, *n + 2), in aggr_add_gpio()
53 return -ENOMEM; in aggr_add_gpio()
55 lookups->table[*n] = GPIO_LOOKUP_IDX(key, hwnum, NULL, *n, 0); in aggr_add_gpio()
58 memset(&lookups->table[*n], 0, sizeof(lookups->table[*n])); in aggr_add_gpio()
60 aggr->lookups = lookups; in aggr_add_gpio()
[all …]
/openbmc/qemu/net/
H A Dslirp.c4 * Copyright (c) 2003-2008 Fabrice Bellard
39 #include "qemu/error-report.h"
42 #include "chardev/char-fe.h"
50 #include "migration/qemu-file-types.h"
52 static int get_str_sep(char *buf, int buf_size, const char **pp, int sep) in get_str_sep()
55 int len; in get_str_sep()
59 return -1; in get_str_sep()
60 len = p1 - p; in get_str_sep()
63 if (len > buf_size - 1) in get_str_sep()
64 len = buf_size - 1; in get_str_sep()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_tc_lib.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2021, Intel Corporation. */
13 * ice_tc_count_lkups - determine lookup count for switch filter
14 * @flags: TC-flower flags
20 static int
24 int lkups_cnt = 1; /* 0th lookup is metadata */ in ice_tc_count_lkups()
27 * - Direction flag (always present) in ice_tc_count_lkups()
28 * - ICE_TC_FLWR_FIELD_VLAN_TPID (present if specified) in ice_tc_count_lkups()
29 * - Tunnel flag (present if tunnel) in ice_tc_count_lkups()
31 if (fltr->direction == ICE_ESWITCH_FLTR_EGRESS) in ice_tc_count_lkups()
[all …]
H A Dice_tc_lib.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2019-2021, Intel Corporation. */
62 } fwd; member
116 /* L2 layer fields with their mask */
123 /* L3 (IPv4[6]) layer fields with their mask */
127 /* L4 layer fields with their mask */
175 * ice_is_chnl_fltr - is this a valid channel filter
176 * @f: Pointer to tc-flower filter
189 if (f->action.fltr_act == ICE_FWD_TO_VSI) in ice_is_chnl_fltr()
190 return f->action.fwd.tc.tc_class >= ICE_CHNL_START_TC && in ice_is_chnl_fltr()
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/openbmc/linux/arch/sparc/include/asm/
H A Dmdesc.h1 /* SPDX-License-Identifier: GPL-2.0 */
40 u64 node, const char *name, int *lenp);
46 * mdesc_for_each_arc(arc, handle, node, MDESC_ARC_TYPE_{FWD,BACK}) {
52 #define MDESC_ARC_TYPE_FWD "fwd"
90 int mdesc_get_node_info(struct mdesc_handle *hp, u64 node,
93 void mdesc_fill_in_cpu_data(cpumask_t *mask);
94 void mdesc_populate_present_mask(cpumask_t *mask);
95 void mdesc_get_page_sizes(cpumask_t *mask, unsigned long *pgsz_mask);
/openbmc/linux/drivers/irqchip/
H A Dirq-bcm7120-l2.c1 // SPDX-License-Identifier: GPL-2.0-only
42 unsigned int n_words;
45 int en_offset[MAX_WORDS];
46 int stat_offset[MAX_WORDS];
51 int num_parent_irqs;
58 struct bcm7120_l2_intc_data *b = data->b; in bcm7120_l2_intc_irq_handle()
60 unsigned int idx; in bcm7120_l2_intc_irq_handle()
64 for (idx = 0; idx < b->n_words; idx++) { in bcm7120_l2_intc_irq_handle()
65 int base = idx * IRQS_PER_WORD; in bcm7120_l2_intc_irq_handle()
67 irq_get_domain_generic_chip(b->domain, base); in bcm7120_l2_intc_irq_handle()
[all …]
H A Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
39 unsigned int n_words;
79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status()
80 unsigned int word) in reg_status()
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status()
86 unsigned int word) in reg_mask_status()
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set()
92 unsigned int word) in reg_mask_set()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
H A Dbrcm,bcm7038-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
23 - Atomic mask/unmask operations
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/openbmc/linux/fs/jfs/
H A Djfs_imap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) International Business Machines Corp., 2000-2004
51 #define IAGFREE_LOCK_INIT(imap) mutex_init(&imap->im_freelock)
52 #define IAGFREE_LOCK(imap) mutex_lock(&imap->im_freelock)
53 #define IAGFREE_UNLOCK(imap) mutex_unlock(&imap->im_freelock)
56 #define AG_LOCK_INIT(imap,index) mutex_init(&(imap->im_aglock[index]))
57 #define AG_LOCK(imap,agno) mutex_lock(&imap->im_aglock[agno])
58 #define AG_UNLOCK(imap,agno) mutex_unlock(&imap->im_aglock[agno])
63 static int diAllocAG(struct inomap *, int, bool, struct inode *);
64 static int diAllocAny(struct inomap *, int, bool, struct inode *);
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/openbmc/u-boot/include/
H A Dfsl_tgec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
17 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
18 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
25 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
26 u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */
27 u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */
29 u32 imask; /* Interrupt mask register */
104 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
109 /* COMMAND_CONFIG - command and configuration register */
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
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/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm7358.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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H A Dbcm7360.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
H A Dbcm7362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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H A Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
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H A Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
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H A Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
H A Dbcm7125.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/openbmc/linux/include/linux/ceph/
H A Dceph_fs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ceph_fs.h - Ceph constants and data types to share between kernel and
6 * Most types in this file are defined as little-endian, and are
20 * subprotocol versions. when specific messages types or high-level
23 * client-facing protocol.
41 /* file -> object mapping */
49 /* pg -> disk layout */
50 __le32 fl_object_stripe_unit; /* UNUSED. for per-object parity, if any */
52 /* object -> pg layout */
53 __le32 fl_unused; /* unused; used to be preferred primary for pg (-1 for none) */
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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vlan.c1 // SPDX-License-Identifier: GPL-2.0+
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask()
12 u32 mask[3]; in sparx5_vlant_set_mask() local
14 /* Divide up mask in 32 bit words */ in sparx5_vlant_set_mask()
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
17 /* Output mask to respective registers */ in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
42 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno) in sparx5_vlan_port_setup()
[all …]
/openbmc/linux/drivers/net/dsa/xrs700x/
H A Dxrs700x.c1 // SPDX-License-Identifier: GPL-2.0
45 unsigned int offset;
47 int stats64_offset;
50 #define XRS700X_MIB_ETHTOOL_ONLY(o, n) {o, n, -1}
86 static void xrs700x_get_strings(struct dsa_switch *ds, int port, in xrs700x_get_strings()
89 int i; in xrs700x_get_strings()
100 static int xrs700x_get_sset_count(struct dsa_switch *ds, int port, int sset) in xrs700x_get_sset_count()
103 return -EOPNOTSUPP; in xrs700x_get_sset_count()
108 static void xrs700x_read_port_counters(struct xrs700x *priv, int port) in xrs700x_read_port_counters()
110 struct xrs700x_port *p = &priv->ports[port]; in xrs700x_read_port_counters()
[all …]
/openbmc/linux/include/linux/
H A Dparport_pc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* --- register definitions ------------------------------- */
9 #define ECONTROL(p) ((p)->base_hi + 0x2)
10 #define CONFIGB(p) ((p)->base_hi + 0x1)
11 #define CONFIGA(p) ((p)->base_hi + 0x0)
12 #define FIFO(p) ((p)->base_hi + 0x0)
13 #define EPPDATA(p) ((p)->base + 0x4)
14 #define EPPADDR(p) ((p)->base + 0x3)
15 #define CONTROL(p) ((p)->base + 0x2)
16 #define STATUS(p) ((p)->base + 0x1)
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_qos.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
17 void enetc_sched_speed_set(struct enetc_ndev_priv *priv, int speed) in enetc_sched_speed_set()
19 struct enetc_hw *hw = &priv->si->hw; in enetc_sched_speed_set()
20 u32 old_speed = priv->speed; in enetc_sched_speed_set()
41 priv->speed = speed; in enetc_sched_speed_set()
46 static int enetc_setup_taprio(struct enetc_ndev_priv *priv, in enetc_setup_taprio()
49 struct enetc_hw *hw = &priv->si->hw; in enetc_setup_taprio()
59 int err; in enetc_setup_taprio()
60 int i; in enetc_setup_taprio()
63 for (i = 0; i < priv->num_tx_rings; i++) in enetc_setup_taprio()
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/openbmc/u-boot/common/
H A Ddlmalloc.c32 #define AlignPage(add) (((add) + (malloc_getpagesize-1)) & \
33 ~(malloc_getpagesize-1))
34 #define AlignPage64K(add) (((add) + (0x10000 - 1)) & ~(0x10000 - 1))
51 static unsigned int gNextAddress = 0;
52 static unsigned int gAddressBase = 0;
53 static unsigned int gAllocatedSize = 0;
63 this->base = bas; in makeGmListElement()
64 this->next = head; in makeGmListElement()
73 assert ( (head == NULL) || (head->base == (void*)gAddressBase)); in gcleanup()
74 if (gAddressBase && (gNextAddress - gAddressBase)) in gcleanup()
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