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/openbmc/linux/arch/x86/include/asm/
H A Dinst.h19 .ifc \r32,%eax
22 .ifc \r32,%ecx
25 .ifc \r32,%edx
28 .ifc \r32,%ebx
31 .ifc \r32,%esp
34 .ifc \r32,%ebp
37 .ifc \r32,%esi
40 .ifc \r32,%edi
44 .ifc \r32,%r8d
47 .ifc \r32,%r9d
[all …]
/openbmc/linux/samples/bpf/
H A Dtest_cls_bpf.sh5 ../pktgen/pktgen_bench_xmit_mode_netif_receive.sh -i $IFC -s 64 \
7 local dropped=`tc -s qdisc show dev $IFC | tail -3 | awk '/drop/{print $7}'`
17 tc qdisc add dev $IFC clsact
18 tc filter add dev $IFC ingress bpf da obj $1 sec $2
26 tc qdisc del dev $IFC clsact
29 IFC=test_veth
31 ip link add name $IFC type veth peer name pair_$IFC
32 ip link set $IFC up
33 ip link set pair_$IFC up
38 ip link del dev $IFC
/openbmc/linux/drivers/memory/
H A Dfsl_ifc.c39 * fsl_ifc_find - find IFC bank
42 * This function walks IFC banks comparing "Base address" field of the CSPR
68 struct fsl_ifc_global __iomem *ifc = ctrl->gregs; in fsl_ifc_ctrl_init() local
73 if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER) in fsl_ifc_ctrl_init()
74 ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat); in fsl_ifc_ctrl_init()
77 ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en); in fsl_ifc_ctrl_init()
80 ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en); in fsl_ifc_ctrl_init()
81 ifc_out32(0x0, &ifc->cm_erattr0); in fsl_ifc_ctrl_init()
82 ifc_out32(0x0, &ifc->cm_erattr1); in fsl_ifc_ctrl_init()
115 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; in check_nand_stat() local
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h30 .ifc \gr,%r0
33 .ifc \gr,%r1
36 .ifc \gr,%r2
39 .ifc \gr,%r3
42 .ifc \gr,%r4
45 .ifc \gr,%r5
48 .ifc \gr,%r6
51 .ifc \gr,%r7
54 .ifc \gr,%r8
57 .ifc \gr,%r9
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dfsl_ifc_nand.c42 /* overview of the fsl ifc controller */
49 void __iomem *addr; /* Address of assigned IFC buffer */
218 * Set up the IFC hardware block and page address fields, and the ifc nand
219 * structure addr field to point to the correct IFC buffer in memory
226 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in set_addr() local
232 ifc_out32(&ifc->ifc_nand.row0, page_addr); in set_addr()
233 ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); in set_addr()
253 * execute IFC NAND command and wait for it to complete
260 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in fsl_ifc_run_command() local
267 ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); in fsl_ifc_run_command()
[all …]
H A Dfsl_ifc_spl.c69 struct fsl_ifc_runtime *ifc = runtime_regs_address(); in nand_wait() local
79 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); in nand_wait()
89 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); in nand_wait()
96 ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); in nand_wait()
110 struct fsl_ifc_runtime *ifc = NULL; in nand_spl_load_image() local
127 ifc = runtime_regs_address(); in nand_spl_load_image()
162 ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); in nand_spl_load_image()
165 ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); in nand_spl_load_image()
169 ifc_out32(&ifc->ifc_nand.nand_fir0, in nand_spl_load_image()
175 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); in nand_spl_load_image()
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dfsl_ifc_nand.c25 for IFC NAND Machine */
40 /* overview of the fsl ifc controller */
45 void __iomem *addr; /* Address of assigned IFC buffer */
136 * Set up the IFC hardware block and page address fields, and the ifc nand
137 * structure addr field to point to the correct IFC buffer in memory
144 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; in set_addr() local
149 ifc_out32(page_addr, &ifc->ifc_nand.row0); in set_addr()
150 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); in set_addr()
170 * execute IFC NAND command and wait for it to complete
178 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; in fsl_ifc_run_command() local
[all …]
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME27 -IFC/Local Bus
28 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
51 - Does not have IFC interface
61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
69 IFC region map from core's view
71 During boot i.e. IFC Region #1:-
75 After relocate to DDR i.e. IFC Region #2:-
77 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
79 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
[all …]
H A Dls2080ardb.c52 * IFC address under 256MB is mapped to 0x30000000, any address above in get_qixis_addr()
356 * IFC and QSPI are muxed on board. in fsl_fdt_fixup_flash()
357 * So disable IFC node in dts if QSPI is enabled or in fsl_fdt_fixup_flash()
379 offset = fdt_path_offset(fdt, "/soc/ifc"); in fsl_fdt_fixup_flash()
382 offset = fdt_path_offset(fdt, "/ifc"); in fsl_fdt_fixup_flash()
392 offset = fdt_path_offset(fdt, "/soc/ifc"); in fsl_fdt_fixup_flash()
395 offset = fdt_path_offset(fdt, "/ifc"); in fsl_fdt_fixup_flash()
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,ifc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
13 NXP's integrated flash controller (IFC) is an advanced version of the
15 interfaces with an extended feature set. The IFC provides access to multiple
24 const: fsl,ifc
44 IFC may have one or two interrupts. If two interrupt specifiers are
64 Child device nodes describe the devices connected to IFC such as NOR (e.g.
65 cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
86 compatible = "fsl,ifc";
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME28 -IFC/Local Bus
29 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
32 - IFC Test Port
62 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
64 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
70 IFC region map from core's view
72 During boot i.e. IFC Region #1:-
77 After relocate to DDR i.e. IFC Region #2:-
79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
81 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
[all …]
/openbmc/u-boot/include/configs/
H A Dls2080a_common.h87 /* IFC */
91 * During booting, IFC is mapped at the region of 0x30000000.
98 * To accommodate bigger NOR flash and other devices, we will map IFC
101 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
103 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
104 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
108 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
109 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
H A Dls1088a_common.h81 /* IFC */
86 * During booting, IFC is mapped at the region of 0x30000000.
93 * To accommodate bigger NOR flash and other devices, we will map IFC
96 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
98 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
99 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
103 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
104 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd9335.yaml48 slim-ifc-dev:
49 description: SLIM IFC device interface
84 - slim-ifc-dev
94 - slim-ifc-dev
110 slim-ifc-dev: false
148 slim-ifc-dev = <&tasha_ifd>;
H A Dqcom,wcd934x.yaml31 slim-ifc-dev:
32 description: IFC device interface
158 - slim-ifc-dev
162 - slim-ifc-dev
183 slim-ifc-dev: false
206 slim-ifc-dev = <&wcd9340_ifd>;
/openbmc/qemu/docs/system/devices/
H A Dcan.rst136 for ifc in /sys/class/net/can* ; do
137 if [ -e $ifc/device/vendor ] ; then
138 if ! grep -q 0x1760 $ifc/device/vendor ; then
144 if [ -e $ifc/device/device ] ; then
145 if ! grep -q 0xff00 $ifc/device/device ; then
151 ifc=$(basename $ifc)
152 /bin/ip link set $ifc type can bitrate 1000000 dbitrate 10000000 fd on
153 /bin/ip link set $ifc up
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DREADME23 -IFC/Local Bus
45 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
46 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
47 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
/openbmc/u-boot/board/freescale/ls1043aqds/
H A DREADME24 -IFC/Local Bus
53 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
54 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
55 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME24 -IFC/Local Bus
53 0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
54 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
55 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dp1010rdb.c79 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; in board_early_init_f() local
80 /* Clock configuration to access CPLD using IFC(GPCM) */ in board_early_init_f()
81 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); in board_early_init_f()
288 /* switch to IFC to read info from CPLD */ in checkboard()
425 "fsl,ifc")) >= 0) { in fdt_del_ifc()
474 /* Delete IFC node as IFC pins are multiplexing with SDHC */ in ft_board_setup()
511 /* mux to IFC to enable CPLD for reset */ in board_reset()
543 else if (hwconfig("ifc")) in misc_init_r()
558 if (strcmp(argv[1], "ifc") == 0) in pin_mux_cmd()
569 "configure multiplexing pin for IFC/SDHC bus in runtime",
H A DREADME.P1010RDB-PB103 SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
115 run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
120 To enable IFC in case of SD boot
122 run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
125 set 'ifc' in hwconfig and save it.
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME51 - Integrated flash controller (IFC) with 16-bit interface
82 - IFC/Local Bus
109 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
110 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
111 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
H A Dls102xa_rcw_sd_ifc.cfg4 #enable IFC, disable QSPI and DSPI
10 #disable IFC, enable QSPI and DSPI
/openbmc/linux/include/linux/
H A Dfsl_ifc.h20 * The actual number of banks implemented depends on the IFC version
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
199 /* reset all IFC hardware */
241 /* IFC Clock Delay */
245 /* Invert IFC clock before sending out */
247 /* Fedback IFC Clock */
678 * IFC Controller NAND Machine registers
742 * IFC controller NOR Machine registers
760 * IFC controller GPCM Machine registers
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME45 - Integrated flash controller (IFC)
64 -IFC/Local Bus
99 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
100 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
108 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB

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