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/openbmc/linux/drivers/video/fbdev/via/
H A Dvia-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for viafb GPIO ports.
9 #include <linux/gpio/driver.h>
10 #include <linux/gpio/machine.h>
12 #include <linux/via-core.h>
14 #include "via-gpio.h"
17 * The ports we know about. Note that the port-25 gpios are not
30 .vg_name = "VGPIO0", /* Guess - not in datasheet */
82 * GPIO access functions
87 struct viafb_gpio_cfg *cfg = gpiochip_get_data(chip); in via_gpio_set() local
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsemtech,sx1501q.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Semtech SX150x GPIO expander
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - semtech,sx1501q
17 - semtech,sx1502q
18 - semtech,sx1503q
19 - semtech,sx1504q
20 - semtech,sx1505q
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/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620-hi4511.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Linaro Ltd.
7 /dts-v1/;
13 compatible = "hisilicon,hi3620-hi4511";
17 stdout-path = "serial0:115200n8";
25 amba-bus {
31 pinctrl-names = "default", "sleep";
32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
33 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
38 pinctrl-names = "default", "sleep";
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/openbmc/u-boot/drivers/gpio/
H A Ddb8500_gpio.c2 * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
3 * The purpose is that GPIO config found in kernel should work by simply
4 * copy-paste it to U-Boot.
11 * Ported to U-Boot by:
29 * The GPIO module in the db8500 Systems-on-Chip is an
37 #define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
60 static void __iomem *get_gpio_addr(unsigned gpio) in get_gpio_addr() argument
62 /* Our list of GPIO chips */ in get_gpio_addr()
75 return gpio_addrs[GPIO_BLOCK(gpio)]; in get_gpio_addr()
78 static unsigned get_gpio_offset(unsigned gpio) in get_gpio_offset() argument
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H A Ds5p_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
14 #include <dm/device-internal.h>
21 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) argument
22 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) argument
24 #define DAT_MASK(gpio) (0x1 << (gpio)) argument
25 #define DAT_SET(gpio) (0x1 << (gpio)) argument
27 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) argument
28 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) argument
30 #define DRV_MASK(gpio) (0x3 << ((gpio) << 1)) argument
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/openbmc/linux/sound/soc/
H A Dsoc-ac97.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ac97.c -- ALSA SoC Audio Layer AC97 support
11 // with code, comments and ideas from :-
17 #include <linux/gpio/consumer.h>
18 #include <linux/gpio/driver.h>
56 return gpio_priv->component; in gpio_to_component()
62 return -EINVAL; in snd_soc_ac97_gpio_request()
72 dev_dbg(component->dev, "set gpio %d to output\n", offset); in snd_soc_ac97_gpio_direction_in()
84 dev_dbg(component->dev, "get gpio %d : %d\n", offset, in snd_soc_ac97_gpio_get()
96 gpio_priv->gpios_set &= ~(1 << offset); in snd_soc_ac97_gpio_set()
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/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dsh_pfc.h105 * - name: Register name (unused, for documentation purposes only)
106 * - r: Physical register address
107 * - r_width: Width of the register (in bits)
108 * - f_width: Width of the fixed-width register fields (in bits)
119 * - name: Register name (unused, for documentation purposes only)
120 * - r: Physical register address
121 * - r_width: Width of the register (in bits)
122 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
150 u32 puen; /* Pull-enable or pull-up control register */
151 u32 pud; /* Pull-up/down control register (optional) */
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dwlf,wm8960.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
22 clock-names:
24 - const: mclk
26 '#sound-dai-cells':
29 AVDD-supply:
32 DBVDD-supply:
35 DCVDD-supply:
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H A Dwlf,wm8903.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
30 - patches@opensource.cirrus.com
39 gpio-controller: true
40 '#gpio-cells':
46 micdet-cfg:
51 micdet-delay:
56 gpio-cfg:
57 $ref: /schemas/types.yaml#/definitions/uint32-array
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H A Dcs42l56.txt5 - compatible : "cirrus,cs42l56"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
14 - cirrus,gpio-nreset : GPIO controller's phandle and the number
15 of the GPIO used to reset the codec.
17 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
24 - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
25 as a pseudo-differential input referenced to AIN1REF/AIN3A.
27 - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured
28 as a pseudo-differential input referenced to AIN2REF/AIN3B.
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H A Dcs42l52.txt5 - compatible : "cirrus,cs42l52"
7 - reg : the I2C address of the device for I2C
11 - cirrus,reset-gpio : GPIO controller's phandle and the number
12 of the GPIO used to reset the codec.
14 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
21 - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
25 - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
29 - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
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/openbmc/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
119 * - name: Register name (unused, for documentation purposes only)
120 * - r: Physical register address
121 * - r_width: Width of the register (in bits)
122 * - f_width: Width of the fixed-width register fields (in bits)
123 * - ids: For each register field (from left to right, i.e. MSB to LSB),
137 * - name: Register name (unused, for documentation purposes only)
138 * - r: Physical register address
139 * - r_width: Width of the register (in bits)
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/openbmc/linux/arch/arm/mach-s3c/
H A Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
11 /* This file contains the necessary definitions to get the basic gpio
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
31 * struct samsung_gpio_cfg GPIO configuration
33 * @get_pull: Read the current pull configuration for the GPIO
34 * @set_pull: Set the current pull configuration for the GPIO
35 * @set_config: Set the current configuration for the GPIO
36 * @get_config: Read the current configuration for the GPIO
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H A Dgpio-samsung.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
16 #include <linux/gpio.h>
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
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H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/libgpiod/
H A Dlibgpiod_2.2.bb3 inherit systemd update-rc.d useradd gobject-introspection
5 LICENSE = "GPL-2.0-or-later & LGPL-2.1-or-later & CC-BY-SA-4.0"
7 file://LICENSES/GPL-2.0-or-later.txt;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
8 file://LICENSES/LGPL-2.1-or-later.txt;md5=4b54a1fd55a448865a0b32d41598759d \
9 file://LICENSES/CC-BY-SA-4.0.txt;md5=fba3b94d88bfb9b81369b869a1e9a20f \
12 FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}-2.x:"
14 SRC_URI += "file://gpio-manager.init"
20 …--enable-tests --enable-tools --enable-bindings-cxx --enable-bindings-glib --enable-gpioset-intera…
21 --disable-tests, \
22 kmod util-linux glib-2.0 catch2 libedit glib-2.0-native libgudev, \
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/openbmc/linux/drivers/regulator/
H A Dgpio-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * gpio-regulator.c
14 * Roger Quadros <ext-roger.quadros@nokia.com>
17 * non-controllable regulators, as well as for allowing testing on
28 #include <linux/regulator/gpio-regulator.h>
29 #include <linux/gpio/consumer.h>
50 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_get_value()
51 if (data->states[ptr].gpios == data->state) in gpio_regulator_get_value()
52 return data->states[ptr].value; in gpio_regulator_get_value()
54 return -EINVAL; in gpio_regulator_get_value()
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H A Dlp8788-buck.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI LP8788 MFD - buck regulator driver
16 #include <linux/gpio.h>
102 struct lp8788_buck1_dvs *dvs = (struct lp8788_buck1_dvs *)buck->dvs; in lp8788_buck1_set_dvs()
108 pinstate = dvs->vsel == DVS_SEL_V0 ? DVS_LOW : DVS_HIGH; in lp8788_buck1_set_dvs()
109 if (gpio_is_valid(dvs->gpio)) in lp8788_buck1_set_dvs()
110 gpio_set_value(dvs->gpio, pinstate); in lp8788_buck1_set_dvs()
115 struct lp8788_buck2_dvs *dvs = (struct lp8788_buck2_dvs *)buck->dvs; in lp8788_buck2_set_dvs()
121 switch (dvs->vsel) { in lp8788_buck2_set_dvs()
142 if (gpio_is_valid(dvs->gpio[0])) in lp8788_buck2_set_dvs()
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H A Dfixed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Roger Quadros <ext-roger.quadros@nokia.com>
13 * non-controllable regulators, as well as for allowing testing on
25 #include <linux/gpio/consumer.h>
52 ret = clk_prepare_enable(priv->enable_clock); in reg_clock_enable()
56 priv->enable_counter++; in reg_clock_enable()
65 clk_disable_unprepare(priv->enable_clock); in reg_clock_disable()
66 priv->enable_counter--; in reg_clock_disable()
74 struct device *dev = rdev->dev.parent; in reg_domain_enable()
77 ret = dev_pm_genpd_set_performance_state(dev, priv->performance_state); in reg_domain_enable()
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/openbmc/linux/drivers/gpio/
H A Dgpio-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio/driver.h>
22 #include <linux/pinctrl/pinconf-generic.h>
27 #include "../pinctrl/pinctrl-rockchip.h"
29 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
30 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
31 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
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/openbmc/linux/drivers/platform/x86/intel/int3472/
H A Dclk_and_regulator.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include <linux/gpio/consumer.h>
16 * 82c0d13a-78c5-4244-9bb1-eb8b539a8d11
18 * through a GPIO.
30 if (clk->ena_gpio) { in skl_int3472_enable_clk()
31 gpiod_set_value_cansleep(clk->ena_gpio, enable); in skl_int3472_enable_clk()
36 args[0].integer.value = clk->imgclk_index; in skl_int3472_enable_clk()
46 acpi_evaluate_dsm(acpi_device_handle(int3472->adev), &img_clk_guid, in skl_int3472_enable_clk()
71 * We're just turning a GPIO on to enable the clock, which operation in skl_int3472_clk_enable()
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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
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H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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/openbmc/linux/drivers/input/touchscreen/
H A Dgoodix.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 2010 - 2012 Goodix Technology.
51 /* Our special handling for GPIO accesses through ACPI is x86 specific */
62 const u8 *cfg, int len);
64 const u8 *cfg, int len);
131 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "YETI-11"),
138 DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"),
151 .ident = "Cube I15-TC",
154 DMI_MATCH(DMI_PRODUCT_NAME, "I15-TC")
162 * goodix_i2c_read - read data from a register of the i2c slave device.
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