/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <maz@kernel.org> 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral 19 - $ref: /schemas/interrupt-controller.yaml# 24 - items: 25 - enum: 26 - qcom,msm8996-gic-v3 [all …]
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/openbmc/linux/drivers/irqchip/ |
H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 2 obj-$(CONFIG_IRQCHIP) += irqchip.o 4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o 5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o 6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o 7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o 8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o 10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o 11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o [all …]
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H A D | irq-gic-v3-its-fsl-mc-msi.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 19 .name = "ITS-fMSI", 33 out_id = of_node ? of_msi_map_id(&mc_dev->dev, of_node, mc_dev->icid) : in fsl_mc_msi_domain_get_msi_id() 34 iort_msi_map_id(&mc_dev->dev, mc_dev->icid); in fsl_mc_msi_domain_get_msi_id() 47 return -EINVAL; in its_fsl_mc_msi_prepare() 50 if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC)) in its_fsl_mc_msi_prepare() 51 return -EINVAL; in its_fsl_mc_msi_prepare() 54 * Set the device Id to be passed to the GIC-ITS: in its_fsl_mc_msi_prepare() 59 info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain, in its_fsl_mc_msi_prepare() [all …]
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H A D | irq-gic-v3-its-platform-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved. 14 .name = "ITS-pMSI", 22 /* Suck the DeviceID out of the msi-parent property */ in of_pmsi_get_dev_id() 26 ret = of_parse_phandle_with_args(dev->of_node, in of_pmsi_get_dev_id() 27 "msi-parent", "#msi-cells", in of_pmsi_get_dev_id() 31 return -EINVAL; in of_pmsi_get_dev_id() 43 return -1; in iort_pmsi_get_dev_id() 53 msi_info = msi_get_domain_info(domain->parent); in its_pmsi_prepare() 55 if (dev->of_node) in its_pmsi_prepare() [all …]
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H A D | irq-gic-v3-its-pci-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved. 27 .name = "ITS-MSI", 61 return -EINVAL; in its_pci_msi_prepare() 63 msi_info = msi_get_domain_info(domain->parent); in its_pci_msi_prepare() 69 * Also tell the ITS that the signalling will come from a proxy in its_pci_msi_prepare() 74 if (alias_dev->subordinate) in its_pci_msi_prepare() 75 pci_walk_bus(alias_dev->subordinate, in its_pci_msi_prepare() 77 info->flags |= MSI_ALLOC_FLAGS_PROXY_DEVICE; in its_pci_msi_prepare() 80 /* ITS specific DeviceID, as the core ITS ignores dev. */ in its_pci_msi_prepare() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/misc/ |
H A D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource 5 network-oriented packet processing applications. After the fsl-mc 12 For an overview of the DPAA2 architecture and fsl-mc bus see: 16 same hardware "isolation context" and a 10-bit value called an ICID 21 between ICIDs and IOMMUs, so an iommu-map property is used to define 28 For arm-smmu binding, see: 32 The msi-map property is used to associate the devices with both the ITS 36 Documentation/devicetree/bindings/interrupt-controller/msi.txt. 38 For GICv3 and GIC ITS bindings, see: 39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. [all …]
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/openbmc/linux/arch/arm64/boot/dts/arm/ |
H A D | foundation-v8-gicv3.dtsi | 8 gic: interrupt-controller@2f000000 { label 9 compatible = "arm,gic-v3"; 10 #interrupt-cells = <3>; 11 #address-cells = <1>; 12 #size-cells = <1>; 14 interrupt-controller; 22 its: msi-controller@2f020000 { label 23 compatible = "arm,gic-v3-its"; 24 msi-controller; 25 #msi-cells = <1>;
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H A D | fvp-base-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0 5 * Architecture Envelope Model (AEM) ARMv8-A 11 /dts-v1/; 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 17 #include "rtsm_ve-motherboard.dtsi" 18 #include "rtsm_ve-motherboard-rs2.dtsi" 22 compatible = "arm,fvp-base-revc", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
H A D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 compatible = "hisilicon,hip05-d02"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 compatible = "arm,psci-0.2"; 22 #address-cells = <1>; 23 #size-cells = <0>; 25 cpu-map { [all …]
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H A D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 compatible = "hisilicon,hip07-d05"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 compatible = "arm,psci-0.2"; 22 #address-cells = <1>; 23 #size-cells = <0>; 25 cpu-map { [all …]
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/openbmc/linux/arch/arm64/boot/dts/cavium/ |
H A D | thunder2-99xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright (c) 2013-2016 Broadcom 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 21 #address-cells = <0x2>; 22 #size-cells = <0x0>; 28 enable-method = "psci"; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 9 gic500: interrupt-controller@1800000 { 10 compatible = "arm,gic-v3"; 11 #address-cells = <2>; 12 #size-cells = <2>; 14 #interrupt-cells = <3>; 15 interrupt-controller; 24 gic_its: gic-its@18200000 { 25 compatible = "arm,gic-v3-its"; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/perf/ |
H A D | arm,smmu-v3-pmcg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <robin.murphy@arm.com> 20 pattern: "^pmu@[0-9a-f]*" 23 - items: 24 - const: arm,mmu-600-pmcg 25 - const: arm,smmu-v3-pmcg [all …]
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/openbmc/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap810-ap0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 /dts-v1/; 14 compatible = "marvell,armada-ap810"; 15 #address-cells = <2>; 16 #size-cells = <2>; 24 compatible = "arm,psci-0.2"; 28 ap810-ap0 { 29 #address-cells = <2>; 30 #size-cells = <2>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am62p-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 9 compatible = "mmio-sram"; 11 #address-cells = <1>; 12 #size-cells = <1>; 16 gic500: interrupt-controller@1800000 { 17 compatible = "arm,gic-v3"; 18 #address-cells = <2>; 19 #size-cells = <2>; 21 #interrupt-cells = <3>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/iommu/ |
H A D | arm,smmu-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 15 revisions, replacing the MMIO register interface with in-memory command 21 pattern: "^iommu@[0-9a-f]*" 23 const: arm,smmu-v3 32 interrupt-names: [all …]
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/openbmc/linux/arch/arm64/boot/dts/amazon/ |
H A D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 model = "Amazon's Annapurna Labs Alpine v3"; 12 compatible = "amazon,al-alpine-v3"; 14 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 #address-cells = <1>; [all …]
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H A D | alpine-v2.dtsi | 2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 16 * - Redistributions of source code must retain the above 20 * - Redistributions in binary form must reproduce the above 35 /dts-v1/; 37 #include <dt-bindings/interrupt-controller/arm-gic.h> 41 compatible = "al,alpine-v2"; 42 #address-cells = <2>; 43 #size-cells = <2>; 46 #address-cells = <2>; [all …]
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/openbmc/qemu/hw/intc/ |
H A D | arm_gicv3.c | 2 * ARM Generic Interrupt Controller v3 (emulation) 33 if (prio != cs->hppi.prio) { in irqbetter() 34 return prio < cs->hppi.prio; in irqbetter() 38 * The same priority IRQ with non-maskable property should signal to in irqbetter() 41 if (nmi != cs->hppi.nmi) { in irqbetter() 49 if (irq <= cs->hppi.irq) { in irqbetter() 59 * of 32), and return a 32-bit integer which has a bit set for each in gicd_int_pending() 64 * + its ENABLE bit is set in gicd_int_pending() 65 * + the GICD enable bit for its group is set in gicd_int_pending() 66 * + its ACTIVE bit is not set (otherwise it would be Active+Pending) in gicd_int_pending() [all …]
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/openbmc/linux/Documentation/virt/kvm/devices/ |
H A D | arm-vgic.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 - KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 13 controller, requiring emulated user-space devices to inject interrupts to the 18 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to 26 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) 27 Base address in the guest physical address space of the GIC distributor 31 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) 32 Base address in the guest physical address space of the GIC virtual cpu 39 -E2BIG Address outside of addressable IPA range 40 -EINVAL Incorrectly aligned address [all …]
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/openbmc/linux/include/kvm/ |
H A D | arm_vgic.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 20 #include <linux/irqchip/arm-gic-v4.h> 28 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 32 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 43 /* same for all guests, as depending only on the _host's_ GIC model */ 45 /* type of the host GIC */ 80 /* GIC system register CPU interface */ 90 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 98 * Per-irq ops overriding some common behavious. 100 * Always called in non-preemptible section and the functions can use [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 5 * Copyright 2017-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 26 #address-cells = <1>; [all …]
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H A D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 6 * Copyright 2017-2020 NXP 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 32 #address-cells = <1>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
H A D | stingray.dtsi | 4 * Copyright(c) 2015-2017 Broadcom. All rights reserved. 16 * * Neither the name of Broadcom nor the names of its 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 37 interrupt-parent = <&gic>; 38 #address-cells = <2>; 39 #size-cells = <2>; 42 #address-cells = <2>; 43 #size-cells = <0>; 47 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; [all …]
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/openbmc/linux/arch/arm64/kvm/vgic/ |
H A D | vgic.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 8 #include <linux/irqchip/arm-gic-common.h> 14 #define VGIC_ADDR_UNDEF (-1) 46 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst, 67 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst, 68 * below macros are defined for ITS table entry encoding. 104 return vcpu->kvm->arch.vgic.implementation_rev; in vgic_get_implementation_rev() 110 if (irq->config == VGIC_CONFIG_EDGE) in irq_is_pending() 111 return irq->pending_latch; in irq_is_pending() 113 return irq->pending_latch || irq->line_level; in irq_is_pending() [all …]
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