Searched full:gateable (Results 1 – 16 of 16) sorted by relevance
33 - description: EIP150 gateable clock34 - description: Main gateable clock
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
7 title: Allwinner A10 Gateable Oscillator Clock
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 - a set of gateable clocks29 gateable clocks.30 - The second cell identifies the particular core clock or gateable41 - Gateable clocks
38 either gateable or ungateable. Some of the CCU dividers can be as well
8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
19 PM domain, and may have a gateable functional clock. Before a device
24 * CP110 has 32 gateable clocks, for the various peripherals in the IP.60 /* A number of gateable clocks need special handling */
243 pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n"); in mvebu_clk_gating_setup()
19 * DOC: basic gateable clock which can gate and ungate its output
268 * device are gateable or not.
108 vice versa. To illustrate consider the simple gateable clk implementation in
888 u8 gate; /* is it independently gateable? */
728 gatable||gateable
227 /* Some SoCs have a gateable clock for the controller */