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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
36 richtek,ld-pulse-delay-us:
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/openbmc/linux/drivers/media/i2c/
H A Drdacm21.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2020 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
21 #include <media/v4l2-async.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-subdev.h>
113 * PCLK polarity - useless due to silicon bug.
119 /* bit[3]=0 - PCLK polarity workaround. */
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H A Drdacm20.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017-2020 Jacopo Mondi
6 * Copyright (C) 2017-2020 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
131 /* fifo_hsync_start = 2*(hts - xres) */
132 { 0x460a, (2 * (OV10635_HTS - OV10635_WIDTH)) >> 8 },
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/openbmc/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 Say yes here to enable debugging support.
38 managed regulators and simple non-configurable regulators.
65 They provide two I2C-controlled DC/DC step-down converters with
66 sleep mode and separate enable pins.
85 tristate "Active-semi act8865 voltage regulator"
90 This driver controls a active-semi act8865 voltage output
94 tristate "Active-semi ACT8945A voltage regulator"
97 This driver controls a active-semi ACT8945A voltage regulator
98 via I2C bus. The ACT8945A features three step-down DC/DC converters
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/openbmc/qemu/target/m68k/
H A Dcpu.c18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
31 cpu->env.pc = value; in m68k_cpu_set_pc()
38 return cpu->env.pc; in m68k_cpu_get_pc()
48 cpu->env.pc = data[0]; in m68k_restore_state_to_opc()
50 cpu->env.cc_op = cc_op; in m68k_restore_state_to_opc()
56 return cs->interrupt_request & CPU_INTERRUPT_HARD; in m68k_cpu_has_work()
61 return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; in m68k_cpu_mmu_index()
66 env->features |= BIT_ULL(feature); in m68k_set_feature()
71 env->features &= ~BIT_ULL(feature); in m68k_unset_feature()
82 if (mcc->parent_phases.hold) { in m68k_cpu_reset_hold()
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/openbmc/linux/arch/m68k/ifpsp060/src/
H A Dftest.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
30 set SREGS, -64
31 set IREGS, -128
32 set IFPREGS, -224
33 set SFPREGS, -320
34 set IFPCREGS, -332
35 set SFPCREGS, -344
36 set ICCR, -346
37 set SCCR, -348
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H A Dfpsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
98 mov.l %d0,-(%sp)
99 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0
100 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
106 mov.l %d0,-(%sp)
107 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0
108 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
114 mov.l %d0,-(%sp)
115 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0
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H A Dpfpsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
97 mov.l %d0,-(%sp)
98 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0
99 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
105 mov.l %d0,-(%sp)
106 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0
107 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
113 mov.l %d0,-(%sp)
114 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0
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