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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
[all …]
/openbmc/linux/drivers/phy/hisilicon/
H A Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
21 #include <dt-bindings/phy/phy.h>
37 int fixed; member
45 void __iomem *mmio; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode()
82 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
88 switch (mode->select) { in histb_combphy_set_mode()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-fixed-mmio.c1 // SPDX-License-Identifier: GPL-2.0
4 * Memory Mapped IO Fixed clock driver
12 #include <linux/clk-provider.h>
21 const char *clk_name = node->name; in fixed_mmio_clk_setup()
29 return ERR_PTR(-EIO); in fixed_mmio_clk_setup()
34 of_property_read_string(node, "clock-output-names", &clk_name); in fixed_mmio_clk_setup()
38 pr_err("%pOFn: failed to register fixed rate clock\n", node); in fixed_mmio_clk_setup()
44 pr_err("%pOFn: failed to add clock provider\n", node); in fixed_mmio_clk_setup()
56 CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
65 clk = fixed_mmio_clk_setup(pdev->dev.of_node); in of_fixed_mmio_clk_probe()
[all …]
/openbmc/linux/arch/arc/boot/dts/
H A Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/openbmc/qemu/hw/misc/
H A Dimx7_ccm.c9 * See the COPYING file in the top-level directory.
27 memset(s->pmu, 0, sizeof(s->pmu)); in imx7_analog_reset()
28 memset(s->analog, 0, sizeof(s->analog)); in imx7_analog_reset()
30 s->analog[ANALOG_PLL_ARM] = 0x00002042; in imx7_analog_reset()
31 s->analog[ANALOG_PLL_DDR] = 0x0060302c; in imx7_analog_reset()
32 s->analog[ANALOG_PLL_DDR_SS] = 0x00000000; in imx7_analog_reset()
33 s->analog[ANALOG_PLL_DDR_NUM] = 0x06aaac4d; in imx7_analog_reset()
34 s->analog[ANALOG_PLL_DDR_DENOM] = 0x100003ec; in imx7_analog_reset()
35 s->analog[ANALOG_PLL_480] = 0x00002000; in imx7_analog_reset()
36 s->analog[ANALOG_PLL_480A] = 0x52605a56; in imx7_analog_reset()
[all …]
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_64.dts1 /dts-v1/;
4 #address-cells = <2>;
5 #size-cells = <2>;
16 stdout-path = "uart0:38400n8";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
29 mmu-type = "riscv,sv39";
30 clock-frequency = <60000000>;
31 d-cache-size = <0x8000>;
[all …]
H A Dae350_32.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
16 stdout-path = "uart0:38400n8";
20 #address-cells = <1>;
21 #size-cells = <0>;
22 timebase-frequency = <60000000>;
29 mmu-type = "riscv,sv32";
30 clock-frequency = <60000000>;
31 d-cache-size = <0x8000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
33 /* 1 GHz fixed main PLL */
35 compatible = "fixed-clock";
[all …]
/openbmc/qemu/docs/devel/
H A Dtcg-icount.rst12 with cycle accurate emulation - QEMU does not attempt to emulate how
15 micro-architecture.
18 incompatible with multi-threaded TCG. It can be used to better align
19 execution time with wall-clock time so a "slow" device doesn't run too
28 is stored in the TimersState of QEMU's timer sub-system. The number of
32 fixed number of ns per instruction or adjusted as execution continues
33 to keep wall clock time and virtual time in sync.
51 Dealing with MMIO
52 -----------------
55 expiry we cannot do the same for MMIO. Every load/store we execute
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/calxeda/
H A Dhb-sregs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Calxeda Highbank system has a block of MMIO registers controlling
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
29 - reg
34 - |
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/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
[all …]
/openbmc/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
27 compatible = "mmio-sram";
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
30 compatible = "arm,cortex-a9-pmu";
31 interrupts-extended = <&mpic 3>;
35 compatible = "marvell,armada380-mbus", "simple-bus";
36 u-boot,dm-pre-reloc;
37 #address-cells = <2>;
[all …]
H A Darmada-375.dtsi6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
68 /* 2 GHz fixed main PLL */
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <1000000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <1000000>;
22 clock-output-names = "v2m:refclk1mhz";
26 compatible = "fixed-clock";
[all …]
H A Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/interconnect/qcom/
H A Dicc-rpm.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/interconnect-provider.h>
16 #include "icc-common.h"
17 #include "icc-rpm.h"
55 struct icc_provider *provider = src->provider; in qcom_icc_set_qnoc_qos()
57 struct qcom_icc_node *qn = src->data; in qcom_icc_set_qnoc_qos()
58 struct qcom_icc_qos *qos = &qn->qos; in qcom_icc_set_qnoc_qos()
61 rc = regmap_update_bits(qp->regmap, in qcom_icc_set_qnoc_qos()
62 qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), in qcom_icc_set_qnoc_qos()
64 qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); in qcom_icc_set_qnoc_qos()
[all …]
/openbmc/linux/sound/soc/sh/
H A Dssi.c1 // SPDX-License-Identifier: GPL-2.0
24 * fixed TDM slot size, regardless of sample resolution.
54 #define CR_BREN (1 << 7) /* clock gating in burst mode */
62 #define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg)))
65 unsigned long mmio; member
71 .mmio = 0xFE680000,
74 .mmio = 0xFE690000,
78 .mmio = 0xFFE70000,
86 * track usage of the SSI; it is simplex-only so prevent attempts of
92 struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; in ssi_startup()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
[all …]
/openbmc/linux/drivers/clocksource/
H A Dtimer-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * Timer 0 is used as free-running clocksource, while timer 1 is
14 * ---
19 * * Armada 370 has no 25 MHz fixed timer.
21 * * Armada XP cannot work properly without such 25 MHz fixed timer as
25 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
68 /* Global timers are connected to the coherency fabric clock, and the
74 * SoC-specific data.
[all …]
/openbmc/linux/drivers/ata/
H A Dsata_sx4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sx4.c - Promise SATA
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2004 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
19 -------------------
29 PATA<->SATA bridges exist on SX4 boards, external to the
34 submitted and waited-on as a single unit), and an optional
39 transactions into a fixed DIMM memory space, from where an ATA
60 This is a very slow, lock-step way of doing things that can
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]

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