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/openbmc/linux/Documentation/gpu/
H A Ddrm-usage-stats.rst1 .. _drm-client-usage-stats:
8 `fops->show_fdinfo()` as part of the driver specific file operations registered
15 output is split between common and driver specific parts. Having said that,
22 - File shall contain one key value pair per one line of text.
23 - Colon character (`:`) must be used to delimit keys and values.
24 - All keys shall be prefixed with `drm-`.
25 - Whitespace between the delimiter and first non-whitespace character shall be
27 - Keys are not allowed to contain whitespace characters.
28 - Numerical key value pairs can end with optional unit string.
29 - Data type of the value is fixed as defined in the specification.
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/openbmc/linux/Documentation/driver-api/dmaengine/
H A Dclient.rst2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsunxi_engine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 * struct sunxi_engine_ops - helper operations for sunXi engines
26 * This callback allows to prepare our engine for an atomic
33 void (*atomic_begin)(struct sunxi_engine *engine,
39 * This callback allows to validate plane-update related CRTC
40 * constraints specific to engines. This is mirroring the
50 int (*atomic_check)(struct sunxi_engine *engine,
62 void (*commit)(struct sunxi_engine *engine);
68 * the layers supported by that engine.
78 struct sunxi_engine *engine);
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/openbmc/linux/Documentation/leds/
H A Dleds-lp55xx.rst8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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/openbmc/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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/openbmc/linux/drivers/leds/
H A Dleds-lp55xx-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Derived from leds-lp5521.c, leds-lp5523.c
15 #include <linux/led-class-multicolor.h>
93 * @reset : Chip specific reset command
94 * @enable : Chip specific enable command
96 * @post_init_device : Chip specific initialization code
101 * @run_engine : Run internal engine for pattern
102 * @dev_attr_group : Device specific attributes
109 /* define if the device has specific initialization process */
127 /* additional device specific attributes */
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/openbmc/linux/Documentation/gpu/amdgpu/
H A Ddriver-core.rst17 the SoC itself rather than specific IPs. E.g., things like GPU resets
23 SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have
32 This was a dedicated IP on older pre-vega chips, but has since
34 have dedicated memory hubs for specific IPs or groups of IPs. We
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
61 This is a multi-purpose DMA engine. The kernel driver uses it for
67 This is the graphics and compute engine, i.e., the block that
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
75 This is the multi-media engine. It handles video and image encode and
76 decode. It's exposed to userspace for user mode drivers (VA-API,
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_heartbeat.c1 // SPDX-License-Identifier: MIT
17 * While the engine is active, we send a periodic pulse along the engine
18 * to check on its health and to flush any idle-barriers. If that request
19 * is stuck, and we fail to preempt it, we declare the engine hung and
20 * issue a reset -- in the hope that restores progress.
23 static bool next_heartbeat(struct intel_engine_cs *engine) in next_heartbeat() argument
28 delay = READ_ONCE(engine->props.heartbeat_interval_ms); in next_heartbeat()
30 rq = engine->heartbeat.systole; in next_heartbeat()
35 * selftests which override the value and expect specific behaviour. in next_heartbeat()
37 * heartbeat periods (or to override the pre-emption timeout as well, in next_heartbeat()
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H A Dintel_engine_pm.c1 // SPDX-License-Identifier: MIT
20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) in intel_gsc_idle_msg_enable() argument
22 struct drm_i915_private *i915 = engine->i915; in intel_gsc_idle_msg_enable()
24 if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { in intel_gsc_idle_msg_enable()
25 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
29 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
40 if (ce->state) { in dbg_poison_ce()
41 struct drm_i915_gem_object *obj = ce->state->obj; in dbg_poison_ce()
42 int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true); in dbg_poison_ce()
50 memset(map, CONTEXT_REDZONE, obj->base.size); in dbg_poison_ce()
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DOperatingSystem.v1_0_2.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
36 "description": "A container engine running in an operating system.",
37 … "longDescription": "This type shall contain a container engine running in an operating system.",
39 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
54 "description": "The URIs to manage this container engine.",
55 "format": "uri-reference",
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/openbmc/qemu/docs/devel/testing/
H A Dblkdebug.rst5 Copyright (C) 2014-2015 Red Hat Inc
8 the COPYING file in the top-level directory.
10 The ``blkdebug`` block driver is a rule-based error injection engine. It can be
17 ----------
23 Error injection allows test cases to trigger I/O errors at specific points.
27 -----
29 engine when to fail an I/O request.
35 follows the same .ini-like format used by QEMU's ``-readconfig`` option, and
41 [inject-error]
47 ``/usr/include/asm-generic/errno-base.h`` for errno values.
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/openbmc/linux/Documentation/powerpc/
H A Dvas-api.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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/openbmc/linux/drivers/dma/ptdma/
H A Dptdma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
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/openbmc/linux/drivers/crypto/marvell/cesa/
H A Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----
536 struct mv_cesa_engine *engine; global() member
631 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine * engine,struct crypto_async_request * req) mv_cesa_engine_enqueue_complete_request() argument
638 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine * engine) mv_cesa_engine_dequeue_complete_request() argument
675 mv_cesa_adjust_op(struct mv_cesa_engine * engine,struct mv_cesa_op_ctx * op) mv_cesa_adjust_op() argument
709 mv_cesa_set_int_mask(struct mv_cesa_engine * engine,u32 int_mask) mv_cesa_set_int_mask() argument
719 mv_cesa_get_int_mask(struct mv_cesa_engine * engine) mv_cesa_get_int_mask() argument
744 struct mv_cesa_engine *engine = cesa_dev->engines + i; mv_cesa_select_engine() local
879 mv_cesa_sg_copy_to_sram(struct mv_cesa_engine * engine,struct scatterlist * sgl,unsigned int nents,unsigned int sram_off,size_t buflen,off_t skip) mv_cesa_sg_copy_to_sram() argument
889 mv_cesa_sg_copy_from_sram(struct mv_cesa_engine * engine,struct scatterlist * sgl,unsigned int nents,unsigned int sram_off,size_t buflen,off_t skip) mv_cesa_sg_copy_from_sram() argument
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/openbmc/linux/drivers/gpu/drm/amd/display/
H A DKconfig1 # SPDX-License-Identifier: MIT
2 menu "Display Engine Configuration"
6 bool "AMD DC - Enable new display engine"
13 Choose this option if you want to use the new display engine
21 has been resolved: https://github.com/llvm/llvm-project/issues/41896.
26 Floating point support, required for DCN-based SoCs
51 This option enables the calculation of crc of specific region via
52 debugfs. Cooperate with specific DMCU FW.
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2P.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2022 HabanaLabs, Ltd.
19 #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
20 #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb"
46 (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
50 (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
58 #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
75 #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
106 (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
141 #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
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/openbmc/linux/Documentation/crypto/
H A Dasync-tx-api.rst1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
69 async_<operation>(<op specific parameters>, struct async_submit_ctl *submit)
72 ------------------------
92 -------------------------
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/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DOperatingSystem_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: OperatingSystem v1.0.2 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2025 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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/openbmc/linux/drivers/net/ethernet/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 for your specific card in the following questions.
35 ports at 10/100 Mbps in full-duplex or half-duplex mode.
70 is needed by any driver which provides HNS acceleration engine or make
71 use of the engine
79 acceleration engine support. The engine is used in Hisilicon hip05,
97 This layer facilitates clients like ENET, RoCE and user-space ethernet
104 tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
109 This selects the HNS3_HCLGE network acceleration engine & its hardware
110 compatibility layer. The engine would be used in Hisilicon hip08 family of
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/openbmc/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_ucode.h1 /* SPDX-License-Identifier: GPL-2.0-only
16 * IE and SE engines can be attached to the same engine group.
35 OTX2_CPT_AE_UC_TYPE = 1, /* AE-MAIN */
36 OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */
42 OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */
94 /* Maximum and current number of engines available for all engine groups */
104 /* Engines reserved to an engine group */
106 int type; /* engine type */
108 int offset; /* constant offset of engine type in the bitmap */
115 * is mirroring enabled, it is set only for engine
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/openbmc/linux/include/linux/mtd/
H A Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
74 * These information are usually used by specific sub-layers to select the
86 * enum nand_page_io_req_type - Direction of an I/O request
96 * struct nand_page_io_req - NAND I/O request object
107 * This object is used to pass per-page I/O requests to NAND sub-layers. This
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/openbmc/openbmc/poky/meta/files/common-licenses/
H A DFTL3 2006-Jan-27
5 Copyright 1996-2002, 2006 by David Turner, Robert Wilhelm, and Werner Lemberg
9 …ive packages; some of them may contain, in addition to the FreeType font engine, various tools and…
11 …r their own explicit license. The license affects thus the FreeType font engine, the test programs…
17 …ware for whatever you want, in parts or full form, without having to pay us. (`royalty-free' usage)
35 … a `program' or `executable'. This program is referred to as `a program using the FreeType engine'.
39 The FreeType Project is copyright (C) 1996-2000 by David Turner, Robert Wilhelm, and Werner Lemberg…
47 This license grants a worldwide, royalty-free, perpetual and irrevocable right and license to use, …
57 … the other for commercial, advertising, or promotional purposes without specific prior written per…
59 …ur documentation or advertising materials: `FreeType Project', `FreeType Engine', `FreeType librar…
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/openbmc/linux/include/uapi/drm/
H A Divpu_accel.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
3 * Copyright (C) 2020-2023 Intel Corporation
76 * struct drm_ivpu_param - Get/Set VPU parameters
85 * PCI Device ID of the VPU device (read-only)
88 * VPU device revision (read-only)
91 * Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
92 * platform type when executing on a simulator or emulator (read-only)
95 * Current PLL frequency (read-only)
98 * Maximum number of simultaneously existing contexts (read-only)
101 * Lowest VPU virtual address available in the current context (read-only)
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/openbmc/linux/drivers/crypto/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 Support for Hisilicon SEC Engine in Hip06 and Hip07
35 Support for HiSilicon SEC Engine of version 2 in crypto subsystem.
50 interface. Specific engine driver may use this module.
75 Support for HiSilicon HPRE(High Performance RSA Engine)

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