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/openbmc/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.c128 static int dpu_wait_stop_done(struct sprd_dpu *dpu) in dpu_wait_stop_done() argument
130 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_stop_done()
143 drm_err(dpu->drm, "dpu wait for stop done time out!\n"); in dpu_wait_stop_done()
150 static int dpu_wait_update_done(struct sprd_dpu *dpu) in dpu_wait_update_done() argument
152 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_update_done()
161 drm_err(dpu->drm, "dpu wait for reg update done time out!\n"); in dpu_wait_update_done()
320 static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state) in sprd_dpu_layer() argument
322 struct dpu_context *ctx = &dpu->ctx; in sprd_dpu_layer()
377 static void sprd_dpu_flip(struct sprd_dpu *dpu) in sprd_dpu_flip() argument
379 struct dpu_context *ctx = &dpu->ctx; in sprd_dpu_flip()
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H A Dsprd_dpu.h23 /* DPU Layer registers offset */
33 * Sprd DPU context structure
35 * @base: DPU controller base address
38 * @vm: videomode structure to use for DPU and DPI initialization
39 * @stopped: indicates whether DPU are stopped
40 * @wait_queue: wait queue, used to wait for DPU shadow register update done and
41 * DPU stop register done interrupt signal.
42 * @evt_update: wait queue condition for DPU shadow register
43 * @evt_stop: wait queue condition for DPU stop register
57 * Sprd DPU device structure
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/openbmc/u-boot/lib/efi_selftest/
H A Defi_selftest_devicepath_util.c17 struct efi_device_path_utilities_protocol *dpu; variable
35 NULL, (void **)&dpu); in setup()
37 dpu = NULL; in setup()
61 node = dpu->create_device_node(DEVICE_PATH_TYPE_MEDIA_DEVICE, in create_single_node_device_path()
67 *dp = dpu->append_device_node(NULL, node); in create_single_node_device_path()
77 len = dpu->get_device_path_size(*dp); in create_single_node_device_path()
102 if (dpu->is_device_path_multi_instance(NULL)) { in execute()
107 len = dpu->get_device_path_size(NULL); in execute()
114 dp1 = dpu->duplicate_device_path(NULL); in execute()
120 dp1 = dpu->append_device_path(NULL, NULL); in execute()
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc7180-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
7 title: Qualcomm Display DPU on SC7180
12 $ref: /schemas/display/msm/dpu-common.yaml#
17 - qcom,sc7180-dpu
18 - qcom,sm6125-dpu
19 - qcom,sm6350-dpu
20 - qcom,sm6375-dpu
68 - qcom,sm6375-dpu
69 - qcom,sm6125-dpu
86 compatible = "qcom,sc7180-dpu";
H A Ddpu-common.yaml3 $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#
6 title: Qualcomm Display DPU common properties
14 Common properties for QCom DPU display controller.
38 Contains the list of output ports from DPU device. These ports
39 connect to interfaces that are external to the DPU hardware,
H A Dqcom,sm6115-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
7 title: Qualcomm Display DPU on SM6115
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm6115-dpu
62 compatible = "qcom,sm6115-dpu";
H A Dqcom,qcm2290-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
7 title: Qualcomm Display DPU on QCM2290
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,qcm2290-dpu
60 compatible = "qcom,qcm2290-dpu";
H A Dqcom,sc7280-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
7 title: Qualcomm Display DPU on SC7280
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sc7280-dpu
62 compatible = "qcom,sc7280-dpu";
H A Dqcom,sm8150-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#
7 title: Qualcomm SM8150 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8150-dpu
53 compatible = "qcom,sm8150-dpu";
H A Dqcom,sdm845-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
7 title: Qualcomm Display DPU on SDM845
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sdm845-dpu
60 compatible = "qcom,sdm845-dpu";
H A Dqcom,msm8998-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
7 title: Qualcomm Display DPU on MSM8998
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,msm8998-dpu
63 compatible = "qcom,msm8998-dpu";
H A Dqcom,sm8250-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
7 title: Qualcomm SM8250 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8250-dpu
60 compatible = "qcom,sm8250-dpu";
H A Dqcom,sm8550-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
7 title: Qualcomm SM8550 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8550-dpu
63 compatible = "qcom,sm8550-dpu";
H A Dqcom,sm8350-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
7 title: Qualcomm SM8350 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8350-dpu
57 compatible = "qcom,sm8350-dpu";
H A Dqcom,sm8450-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
7 title: Qualcomm SM8450 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8450-dpu
64 compatible = "qcom,sm8450-dpu";
H A Dqcom,sc8280xp-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
15 $ref: /schemas/display/msm/dpu-common.yaml#
19 const: qcom,sc8280xp-dpu
60 compatible = "qcom,sc8280xp-dpu";
/openbmc/linux/Documentation/devicetree/bindings/display/sprd/
H A Dsprd,sharkl3-dpu.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
7 title: Unisoc Sharkl3 Display Processor Unit (DPU)
13 DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
19 const: sprd,sharkl3-dpu
63 dpu: dpu@63000000 {
64 compatible = "sprd,sharkl3-dpu";
/openbmc/linux/drivers/vdpa/solidrun/
H A Dsnet_ctrl.c3 * SolidRun DPU driver for control plane
34 /* Control register used to read data from the DPU */
112 /* Wait until the DPU finishes completely. in snet_wait_for_dpu_completion()
118 /* Reading ctrl from the DPU:
123 * (1) Verify that the DPU is not in the middle of another operation by
184 SNET_WARN(pdev, "Error while reading control data from DPU, err %d\n", ret); in snet_ctrl_read_from_dpu()
208 SNET_WARN(pdev, "Timeout waiting for the DPU to complete a control command\n"); in snet_ctrl_read_from_dpu()
215 /* Send a control message to the DPU using the old mechanism
227 * Make sure that the opcode register is empty, and that the DPU isn't in snet_send_ctrl_msg_old()
239 /* DPU ACKs the message by clearing the opcode register */ in snet_send_ctrl_msg_old()
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_rm.h17 * struct dpu_rm - DPU dynamic hardware resource manager
41 * @rm: DPU Resource Manager handle
54 * @rm: DPU Resource Manager handle
66 * @rm: DPU Resource Manager handle
81 * @rm: DPU Resource Manager handle
97 * @rm: DPU Resource Manager handle
107 * @rm: DPU Resource Manager handle
117 * @rm: DPU Resource Manager handle
H A Ddpu_vbif.h47 * @dpu_kms: DPU handler
55 * @dpu_kms: DPU handler
63 * @dpu_kms: DPU handler
69 * @dpu_kms: DPU handler
H A Ddpu_kms.h43 #define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__)
44 #define DPU_ERROR_RATELIMITED(fmt, ...) pr_err_ratelimited("[dpu error]" fmt, ##__VA_ARGS__)
160 * @dpu_kms: pointer to dpu kms structure
172 * @dpu_kms: Pointer to DPU's KMS structure
174 * Return: dentry pointer for DPU's debugfs location
179 * DPU info management functions
H A Ddpu_formats.h13 * dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
25 * @format: dpu format
26 * @supported_formats: supported formats by dpu HW
59 * dpu non-standard, i.e. modified format
H A Ddpu_core_irq.h34 * @dpu_kms: DPU handle
45 * @dpu_kms: DPU handle
62 * @dpu_kms: DPU handle
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A Dpipeline.json10 …"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB…
15 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being proce…
20 …"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being p…
25 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json9 …n issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and the…
12 …n issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and the…
15 …ion issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and the…
18 …ion issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and the…
21 …ed due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and the…
24 …ed due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and the…

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