/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra124-dpaux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two 15 pins which can be assigned to either the DPAUX channel or to an I2C 18 When configured for DisplayPort AUX operation, the DPAUX controller 24 pattern: "^dpaux@[0-9a-f]+$" [all …]
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H A D | nvidia,tegra124-sor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 19 pattern: "^sor@[0-9a-f]+$" 23 - enum: 24 - nvidia,tegra124-sor 25 - nvidia,tegra210-sor [all …]
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/openbmc/linux/drivers/gpu/drm/tegra/ |
H A D | dpaux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/io.h> 12 #include <linux/pinctrl/pinconf-generic.h> 26 #include "dpaux.h" 76 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, in tegra_dpaux_readl() argument 79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl() 81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl() 86 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, in tegra_dpaux_writel() argument 89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel() 90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel() [all …]
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H A D | sor.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 9 #include <linux/io.h> 486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() 488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl() 496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel() 497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel() 504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock() 506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock() 510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock() [all …]
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/openbmc/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra194-clock.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 8 #include <dt-bindings/power/tegra194-powergate.h> 9 #include <dt-bindings/reset/tegra194-reset.h> 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h> [all …]
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H A D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra210-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/reset/tegra210-car.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/tegra124-soctherm.h> 10 #include <dt-bindings/soc/tegra-pmc.h> [all …]
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H A D | tegra186.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra186-clock.h> 3 #include <dt-bindings/gpio/tegra186-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/memory/tegra186-mc.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8 #include <dt-bindings/power/tegra186-powergate.h> 9 #include <dt-bindings/reset/tegra186-reset.h> 10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h> [all …]
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H A D | tegra186-p3509-0000+p3636-0001.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/mfd/max77620.h> 12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186"; 30 stdout-path = "serial0:115200n8"; 41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>; 42 phy-handle = <&phy>; 43 phy-mode = "rgmii-id"; [all …]
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H A D | tegra194-p2972-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 7 #include "tegra194-p2888.dtsi" 11 compatible = "nvidia,p2972-0000", "nvidia,tegra194"; 24 #address-cells = <1>; 25 #size-cells = <0>; 31 remote-endpoint = <&xbar_i2s1_ep>; 39 dai-format = "i2s"; [all …]
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H A D | tegra132-norrin.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 30 vdd-supply = <&vdd_3v3_hdmi>; 31 pll-supply = <&vdd_hdmi_pll>; 32 hdmi-supply = <&vdd_5v0_hdmi>; 34 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 35 nvidia,hpd-gpio = 42 avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; [all …]
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H A D | tegra210-p3450-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/gpio-keys.h> 5 #include <dt-bindings/input/linux-event-codes.h> 6 #include <dt-bindings/mfd/max77620.h> 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 22 stdout-path = "serial0:115200n8"; 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; [all …]
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H A D | tegra186-p2771-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 7 #include "tegra186-p3310.dtsi" 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 23 #address-cells = <1>; 24 #size-cells = <0>; 30 remote-endpoint = <&xbar_i2s1_ep>; 38 dai-format = "i2s"; [all …]
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H A D | tegra194-p3509-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 19 #address-cells = <1>; 20 #size-cells = <0>; 26 remote-endpoint = <&xbar_i2s3_ep>; 34 dai-format = "i2s"; 45 #address-cells = <1>; 46 #size-cells = <0>; [all …]
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H A D | tegra210-smaug.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/mfd/max77620.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 12 compatible = "google,smaug-rev8", "google,smaug-rev7", 13 "google,smaug-rev6", "google,smaug-rev5", 14 "google,smaug-rev4", "google,smaug-rev3", 15 "google,smaug-rev2", "google,smaug-rev1", 25 stdout-path = "serial0:115200n8"; [all …]
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H A D | tegra210-p2597.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 16 dpaux@54040000 { 23 avdd-dsi-csi-supply = <&vdd_dsi_csi>; 33 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 34 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 35 hdmi-supply = <&vdd_hdmi>; 37 nvidia,ddc-i2c-bus = <&hdmi_ddc>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 14 stdout-path = "serial0:115200n8"; 20 * missing a unit-address. However, the bootloader on these Chromebook 22 * Adding the unit-address causes the bootloader to create a /memory 34 /delete-node/ memory@80000000; 40 vdd-supply = <&vdd_3v3_hdmi>; 41 pll-supply = <&vdd_hdmi_pll>; 42 hdmi-supply = <&vdd_5v0_hdmi>; [all …]
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H A D | tegra124-venice2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 18 stdout-path = "serial0:115200n8"; 29 vdd-supply = <&vdd_3v3_hdmi>; 30 pll-supply = <&vdd_hdmi_pll>; 31 hdmi-supply = <&vdd_5v0_hdmi>; 33 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34 nvidia,hpd-gpio = 41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; [all …]
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/openbmc/u-boot/drivers/video/tegra124/ |
H A D | dp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2011-2013, NVIDIA Corporation. 13 #include <asm/io.h> 14 #include <asm/arch-tegra/dc.h> 27 * struct tegra_dp_priv - private displayport driver info 43 return readl((u32 *)dp->regs + reg); in tegra_dpaux_readl() 49 writel(val, (u32 *)dp->regs + reg); in tegra_dpaux_writel() 64 timeout_us -= poll_interval_us; in tegra_dc_dpaux_poll_register() 84 debug("dp: DPAUX transaction timeout\n"); in tegra_dpaux_wait_transaction() 85 return -1; in tegra_dpaux_wait_transaction() [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2013-2015 10 #include <asm/io.h> 14 #include <asm/arch-tegra/clk_rst.h> 15 #include <asm/arch-tegra/timer.h> 49 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 57 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 122 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 320 * SPDIF - which is both 0x08 and 0x0c 323 #define NONE(name) (-1) [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2013-2015 11 #include <asm/io.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/timer.h> 50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 59 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 350 * SPDIF - which is both 0x08 and 0x0c 353 #define NONE(name) (-1) [all …]
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 14 #include <dt-bindings/clock/tegra124-car.h> 15 #include <dt-bindings/reset/tegra124-car.h> 18 #include "clk-id.h" 95 #define MASK(x) (BIT(x) - 1) 995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, 1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init() [all …]
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H A D | clk-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved. 6 #include <linux/io.h> 8 #include <linux/clk-provider.h> 17 #include <dt-bindings/clock/tegra210-car.h> 18 #include <dt-bindings/reset/tegra210-car.h> 23 #include "clk-id.h" 264 * SDM fractional divisor is 16-bit 2's complement signed number within 265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned 266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to [all …]
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/openbmc/linux/ |
H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz' 2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz' 3 2024-12-2 [all...] |
H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms) 2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c' 3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms) 4 2024-1 [all...] |