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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dmediatek,mtk-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The watchdog supports a pre-timeout interrupt that fires
14 timeout-sec/2 before the expiry.
17 - $ref: watchdog.yaml#
22 - enum:
23 - mediatek,mt2712-wdt
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195-cherry-tomato-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8195-cherry.dtsi"
9 model = "Acer Tomato (rev3 - 4) board";
10 compatible = "google,tomato-rev4", "google,tomato-rev3",
16 realtek,amic-delay-ms = <250>;
20 pins-low-power-hdmi-disable {
26 input-enable;
27 bias-pull-down;
30 pins-low-power-pcie0-disable {
[all …]
H A Dmt8195-cherry-tomato-r2.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8195-cherry.dtsi"
10 compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";
15 realtek,btndet-delay = <16>;
19 pins-low-power-hdmi-disable {
25 input-enable;
26 bias-pull-down;
29 pins-low-power-pcie0-disable {
33 input-enable;
[all …]
H A Dmt8195-cherry-tomato-r1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8195-cherry.dtsi"
10 compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";
15 realtek,btndet-delay = <16>;
28 /delete-property/ mediatek,disable-extrst;
H A Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2400-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2400-scu", "syscon", "simple-mfd"
24 const: aspeed,ast2400-pinctrl
29 $ref: pinmux-node.yaml#
34 bias-disable: true
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/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 * C5 is a multi-signal pin (high and low priority signals). Here we touch
41 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
45 * E19 is a single-signal pin with two functions that influence the active
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H A Dpinctrl-aspeed-g4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/pinctrl/pinconf-generic.h>
20 #include "../pinctrl-utils.h"
21 #include "pinmux-aspeed.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
45 #define SCU84 0x84 /* Multi-function Pin Control #2 */
46 #define SCU88 0x88 /* Multi-function Pin Control #3 */
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/openbmc/linux/drivers/watchdog/
H A Dmtk_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6735-wdt.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
15 #include <dt-bindings/reset/mt7986-resets.h>
16 #include <dt-bindings/reset/mt8183-resets.h>
17 #include <dt-bindings/reset/mt8186-resets.h>
18 #include <dt-bindings/reset/mt8188-resets.h>
19 #include <dt-bindings/reset/mt8192-resets.h>
20 #include <dt-bindings/reset/mt8195-resets.h>
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