| /openbmc/linux/drivers/cpufreq/ |
| H A D | kirkwood-cpufreq.c | 22 struct clk *ddr_clk; member
68 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
134 priv.ddr_clk = of_clk_get_by_name(np, "ddrclk"); in kirkwood_cpufreq_probe()
135 if (IS_ERR(priv.ddr_clk)) { in kirkwood_cpufreq_probe()
137 err = PTR_ERR(priv.ddr_clk); in kirkwood_cpufreq_probe()
141 err = clk_prepare_enable(priv.ddr_clk); in kirkwood_cpufreq_probe()
146 kirkwood_freq_table[1].frequency = clk_get_rate(priv.ddr_clk) / 1000; in kirkwood_cpufreq_probe()
172 clk_disable_unprepare(priv.ddr_clk); in kirkwood_cpufreq_probe()
186 clk_disable_unprepare(priv.ddr_clk); in kirkwood_cpufreq_remove()
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 206 u64 ddr_clk = priv->phy_clk; in rk_mipi_phy_enable() local
233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable()
244 if (ddr_clk / (MHz) <= freq_rang[i][0]) in rk_mipi_phy_enable()
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable()
274 if ((ddr_clk * i % refclk < remain) && in rk_mipi_phy_enable()
275 (ddr_clk * i / refclk) < max_fbdiv) { in rk_mipi_phy_enable()
277 remain = ddr_clk * i % refclk; in rk_mipi_phy_enable()
280 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
281 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
282 priv->phy_clk = ddr_clk; in rk_mipi_phy_enable()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | microchip,lan966x-gck.yaml | 14 ddr_clk and sys_clk. This clock controller generates and supplies
56 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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| H A D | imx7ulp-pcc-clock.yaml | 67 - const: ddr_clk
106 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ram.c | 26 unsigned long ddr_clk; in stm32mp1_ddr_clk_enable() local
49 ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); in stm32mp1_ddr_clk_enable()
50 if (ddr_clk > (mem_speed * 1000 * 100)) { in stm32mp1_ddr_clk_enable()
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| /openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
| H A D | clk.c | 80 /* DDR_CLK = PLLOUT / DDR_POST_DIV */ in get_clocks()
88 /* AHB_CLK = DDR_CLK / AHB_POST_DIV */ in get_clocks()
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | clocks-common.c | 269 u32 ddr_clk, sys_clk_khz, omap_rev, divider; in omap_ddr_clk() local
280 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / in omap_ddr_clk()
297 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
298 ddr_clk *= 1000; /* convert to Hz */ in omap_ddr_clk()
299 debug("ddr_clk %d\n ", ddr_clk); in omap_ddr_clk()
301 return ddr_clk; in omap_ddr_clk()
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx7ulp.c | 29 static const char * const nic_sels[] = { "firc", "ddr_clk", };
30 static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "a…
115 …hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK… in imx7ulp_clk_scg1_init()
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| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | clk.c | 63 /* DDR_CLK = PLLOUT / DDR_POST_DIV */ in get_clocks()
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| H A D | lowlevel_init.S | 67 * DDR_CLK = PLLOUT / DDR_POST_DIV
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| /openbmc/u-boot/drivers/ram/aspeed/ |
| H A D | sdram_ast2500.c | 84 struct clk ddr_clk; member
439 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in ast2500_sdrammc_probe()
485 clk_set_rate(&priv->ddr_clk, priv->clock_rate); in ast2500_sdrammc_probe()
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| H A D | sdram_ast2600.c | 197 struct clk ddr_clk; member
962 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in ast2600_sdrammc_probe()
967 clk_set_rate(&priv->ddr_clk, priv->clock_rate); in ast2600_sdrammc_probe()
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| /openbmc/linux/arch/arm/boot/dts/microchip/ |
| H A D | lan966x.dtsi | 50 ddr_clk: ddr_clk { label
66 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | vlv_dsi_pll.c | 384 u32 ddr_clk = 0; in glk_dsi_program_esc_clock() local
394 ddr_clk = dsi_rate / 2; in glk_dsi_program_esc_clock()
397 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000); in glk_dsi_program_esc_clock()
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| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear6xx_clock.c | 277 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, in spear6xx_clk_init()
280 clk_register_clkdev(clk, "ddr_clk", NULL); in spear6xx_clk_init()
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 35 struct clk ddr_clk; member
690 ret = clk_set_rate(&dram->ddr_clk, in sdram_init()
802 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
803 ret = clk_request(dev_clk, &priv->ddr_clk); in rk322x_dmc_probe()
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| H A D | sdram_rk3188.c | 36 struct clk ddr_clk; member
722 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
906 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
907 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3188_dmc_probe()
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| H A D | dmc-rk3368.c | 24 struct clk ddr_clk; member
807 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); in setup_sdram()
939 priv->ddr_clk.id = CLK_DDR; in rk3368_dmc_probe()
940 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3368_dmc_probe()
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| H A D | sdram_rk3288.c | 38 struct clk ddr_clk; member
797 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
1071 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()
1072 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3288_dmc_probe()
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| H A D | sdram_rk3399.c | 35 struct clk ddr_clk; member
1165 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); in rk3399_dmc_init()
1167 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in rk3399_dmc_init()
1173 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); in rk3399_dmc_init()
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx7ulp.dtsi | 282 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
314 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-shx3.c | 108 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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| H A D | clock-sh7785.c | 125 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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| H A D | clock-sh7786.c | 133 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
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| /openbmc/linux/arch/mips/lantiq/xway/ |
| H A D | clk.c | 302 /* fpi clock is derived from ddr_clk */ in ltq_grx390_fpi_hz()
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