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/openbmc/linux/drivers/auxdisplay/
H A Dhd44780.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
6 * Copyright (C) 2016-2017 Glider bvba
38 struct gpio_desc *pins[PIN_NUM]; member
43 struct hd44780_common *hdc = lcd->drvdata; in hd44780_backlight()
44 struct hd44780 *hd = hdc->hd44780; in hd44780_backlight()
46 if (hd->pins[PIN_CTRL_BL]) in hd44780_backlight()
47 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_BL], on); in hd44780_backlight()
52 /* Maintain the data during 20 us before the strobe */ in hd44780_strobe_gpio()
55 gpiod_set_value_cansleep(hd->pins[PIN_CTRL_E], 1); in hd44780_strobe_gpio()
[all …]
H A Dpanel.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
11 * serial module compatible with Samsung's KS0074. The pins may be connected in
14 * The keypad consists in a matrix of push buttons connecting input pins to
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
26 gpb: gpb-gpio-bank {
[all …]
H A Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
16 samsung,pins = #_pin; \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-sbc-t43.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
6 #include "am437x-cm-t43.dts"
7 #include "compulab-sb-som.dtsi"
10 model = "CompuLab CM-T43 on SB-SOM-T43";
11 compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
19 mmc1_pins: mmc1-pins {
20 pinctrl-single,pins = <
32 dss_pinctrl_default: dss-pinctrl-default-pins {
33 pinctrl-single,pins = <
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
96 #define PIN_BANK_4BIT(pins, reg, id) \ argument
100 .nr_pins = pins, \
105 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ argument
109 .nr_pins = pins, \
112 .eint_mask = (1 << (pins)) - 1, \
117 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ argument
[all …]
H A Dpinctrl-exynos.h1 /* SPDX-License-Identifier: GPL-2.0+ */
54 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ argument
58 .nr_pins = pins, \
63 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
67 .nr_pins = pins, \
73 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
77 .nr_pins = pins, \
83 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ argument
87 .nr_pins = pins, \
93 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ argument
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 interrupt-parent = <&intc>;
17 #address-cells = <2>;
[all …]
H A Dsc8280xp-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sc8280xp-pmics.dtsi"
17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
26 compatible = "pwm-backlight";
28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
29 power-supply = <&vreg_edp_bl>;
31 pinctrl-names = "default";
[all …]
H A Dsc7180-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include "sc7180-firmware-tfa.dtsi"
20 compatible = "qcom,sc7180-idp", "qcom,sc7180";
30 stdout-path = "serial0:115200n8";
42 /delete-node/ &hyp_mem;
43 /delete-node/ &xbl_mem;
[all …]
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzv2m.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
34 #define DRV_NAME "pinctrl-rzv2m"
60 * n indicates number of pins in the port, a is the register index
118 struct pinctrl_pin_desc *pins; member
120 const struct rzv2m_pinctrl_data *data; member
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5.dtsi2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
22 interrupt-parent = <&aic>;
45 compatible = "arm,arm926ej-s";
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
[all …]
/openbmc/u-boot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Socionext Inc.
19 - 1)
26 - 1)
44 static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data) in uniphier_pin_get_drvctrl() argument
46 return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK; in uniphier_pin_get_drvctrl()
49 static inline unsigned int uniphier_pin_get_drv_type(unsigned int data) in uniphier_pin_get_drv_type() argument
51 return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) & in uniphier_pin_get_drv_type()
56 * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
59 * @data: additional per-pin data
[all …]
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (C) 2009 - 2012 Paul Mundt
12 #define DRV_NAME "sh-pfc"
65 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { in sh_pfc_get_pin_index()
66 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; in sh_pfc_get_pin_index()
68 if (pin <= range->end) in sh_pfc_get_pin_index()
69 return pin >= range->start in sh_pfc_get_pin_index()
70 ? offset + pin - range->start : -1; in sh_pfc_get_pin_index()
72 offset += range->end - range->start + 1; in sh_pfc_get_pin_index()
75 return -EINVAL; in sh_pfc_get_pin_index()
[all …]
/openbmc/linux/drivers/pinctrl/vt8500/
H A Dpinctrl-wmt.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-wmt.h"
26 static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_setbits() argument
31 val = readl_relaxed(data->base + reg); in wmt_setbits()
33 writel_relaxed(val, data->base + reg); in wmt_setbits()
36 static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_clearbits() argument
41 val = readl_relaxed(data->base + reg); in wmt_clearbits()
43 writel_relaxed(val, data->base + reg); in wmt_clearbits()
75 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); in wmt_pmx_get_function_groups() local
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-nsa320.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
9 /dts-v1/;
11 #include "kirkwood-nsa3x0-common.dtsi"
15 compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood";
24 stdout-path = &uart0;
28 pinctrl: pin-controller@10000 {
29 pinctrl-names = "default";
31 /* SATA Activity and Present pins are not connected */
32 pmx_sata0: pmx-sata0 {
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-lantiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
17 #include "pinctrl-lantiq.h"
22 return info->num_grps; in ltq_get_group_count()
29 if (selector >= info->num_grps) in ltq_get_group_name()
31 return info->grps[selector].name; in ltq_get_group_name()
36 const unsigned **pins, in ltq_get_group_pins() argument
40 if (selector >= info->num_grps) in ltq_get_group_pins()
41 return -EINVAL; in ltq_get_group_pins()
[all …]
H A Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <linux/firmware/xlnx-zynqmp.h>
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
47 * struct zynqmp_pmux_function - a pinmux function
62 * struct zynqmp_pinctrl - driver data
69 * This struct is stored as driver data and used to retrieve
71 * group pins.
82 * struct zynqmp_pctrl_group - Pin control group info
[all …]
H A Dpinctrl-single.c25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
102 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
103 * @offset: offset base of pins
104 * @npins: number pins with the same mux value of gpio function
[all …]
/openbmc/linux/sound/soc/
H A Dsoc-jack.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-jack.c -- ALSA SoC jack handling
21 * snd_soc_jack_report - Report the current status for a jack
28 * DAPM pins will be enabled or disabled as appropriate and DAPM
40 if (!jack || !jack->jack) in snd_soc_jack_report()
44 dapm = &jack->card->dapm; in snd_soc_jack_report()
46 mutex_lock(&jack->mutex); in snd_soc_jack_report()
48 jack->status &= ~mask; in snd_soc_jack_report()
49 jack->status |= status & mask; in snd_soc_jack_report()
53 list_for_each_entry(pin, &jack->pins, list) { in snd_soc_jack_report()
[all …]
/openbmc/linux/Documentation/driver-api/media/drivers/
H A Dbttv-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -------------------------
15 bttv-cards.c, which holds the information required for each board.
24 example. The file Documentation/admin-guide/media/bttv-cardlist.rst has a list
48 Below is a do-it-yourself description for you.
50 The bt8xx chips have 32 general purpose pins, and registers to control
51 these pins. One register is the output enable register
52 (``BT848_GPIO_OUT_EN``), it says which pins are actively driven by the
53 bt848 chip. Another one is the data register (``BT848_GPIO_DATA``), where
54 you can get/set the status if these pins. They can be used for input
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdc4_gpios: sdc4-gpios {
6 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
11 sdcc1_pins: sdcc1-pin-active {
13 pins = "sdc1_clk";
14 drive-strengh = <16>;
15 bias-disable;
19 pins = "sdc1_cmd";
20 drive-strengh = <10>;
21 bias-pull-up;
[all …]
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 /* Group the pins by the driving current */
62 * struct mtk_pin_field - the structure that holds the information of the field
78 * struct mtk_pin_field_calc - the structure that holds the range providing
86 * @x_bits: the bit distance between two consecutive pins within
89 * @fixed: the consecutive pins share the same bits with the 1st
104 * struct mtk_pin_reg_calc - the structure that holds all ranges used to
116 * struct mtk_pin_desc - the structure that providing information
129 * struct mtk_group_desc - generic pin group descriptor
131 * @pins: array of pins that belong to the group
[all …]
/openbmc/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32cc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2017-2022 NXP
7 * Copyright 2015-2016 Freescale Semiconductor, Inc.
28 #include "../pinctrl-utils.h"
29 #include "pinctrl-s32.h"
88 * @gpio_configs: Saved configurations for GPIO pins
109 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; in s32_get_region()
113 pin_range = ipctl->regions[i].pin_range; in s32_get_region()
114 if (pin >= pin_range->start && pin <= pin_range->end) in s32_get_region()
115 return &ipctl->regions[i]; in s32_get_region()
[all …]

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