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/openbmc/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
H A Dev6-memchr.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
45 addq $18,$16,$6 /* E0 */
47 xor $16,$6,$1 /* E0 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
H A Dev6-copy_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
13 -----------------------------
24 that the processor can fetch at most 4 aligned instructions per cycle.
28 9 cycles but I was not able to get it to run that fast -- the initial
34 -------------------------------------
45 --------------------------------------
51 forced me to add another cycle to the inner-most kernel - up to 11
53 further by unrolling the loop and doing multiple prefetches per cycle.
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
[all …]
/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dmax31790.rst10 Addresses scanned: -
18 -----------
24 through the I2C interface. The outputs drive "4-wire" fans directly,
28 Tachometer inputs monitor fan tachometer logic outputs for precise (+/-1%)
35 -------------
38 fan[1-12]_input RO fan tachometer speed in RPM
39 fan[1-12]_fault RO fan experienced fault
40 fan[1-6]_target RW desired fan speed in RPM
41 fan[1-6]_enable RW enable or disable the tachometer input
42 pwm[1-6]_enable RW regulator mode, 0=disabled (duty cycle=0%), 1=manual mode, 2=rpm mode
[all …]
/openbmc/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
44 #define RZ_MTU3_TIOR 6 /* Timer I/O control register */
45 #define RZ_MTU3_TIORH 6 /* Timer I/O control register H */
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * STATIC_TRAINING - Set only if static parameters for training are set and
29 /*6 */
49 /*6 */
56 /*center DQS on read cycle */
82 /*6 */
102 /*6 */
122 /*6 */
129 /*center DQS on read cycle */
155 /*6 2 4 19 */
[all …]
/openbmc/linux/drivers/ata/
H A Dlibata-pata-timings.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
22 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
[all …]
H A Dpata_icside.c1 // SPDX-License-Identifier: GPL-2.0-only
35 .stepping = 6,
41 .stepping = 6,
47 .stepping = 6,
80 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
82 /* ---------------- Version 5 PCB Support Functions --------------------- */
88 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqenable_arcin_v5()
90 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqenable_arcin_v5()
98 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqdisable_arcin_v5()
100 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqdisable_arcin_v5()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-sl28cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
18 * | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns |
19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
[all …]
/openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-powercycle3 # shellcheck source=meta-facebook/meta-minerva/recipes-minerva/plat-tool/files/minerva-common-funct…
4 source /usr/libexec/minerva-common-functions
6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle
8 cmm-hsc-power-cycle() {
13 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
23 ret1=$(i2cset -y -f 0 0x44 0xfd 0x00)
24 ret2=$(i2cset -y -f 0 0x44 0xfd 0x0b)
27 ret3=$(i2cset -f -y 0 0x43 0xec)
29 if [ "$ret3" -ne 0 ] && { [ "$ret1" -ne 0 ] || [ "$ret2" -ne 0 ]; }; then
37 compute-blade-hsc-power-control() {
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
36 # bit4: 0, addr/cmd in smame cycle
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3430-sdp.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
20 clock-frequency = <2600000>;
32 vmmc-supply = <&vmmc1>;
33 vqmmc-supply = <&vsim>;
35 * S6-3 must be in ON position for 8 bit mode to function
38 bus-width = <8>;
55 compatible = "cfi-flash";
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
42 #define ISR_RXFIFO (1 << 6) /* rx to fifo */
63 #define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
66 #define MACCR_LOOPBACK (1 << 3) /* loop-back */
83 /* Tx Cycle Length */
88 /* Tx Interrupt Timeout = n * Tx Cycle */
90 /* Rx Cycle Length */
95 /* Rx Interrupt Timeout = n * Rx Cycle */
105 /* Tx Cycle Length */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.txt4 external memory (such as NAND or other memory-mapped peripherals) whereas
10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
11 (CS0 thru CS5) so that in theory 6 different devices can be connected.
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
[all …]
/openbmc/linux/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
36 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg2 # Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
9 # SPDX-License-Identifier: GPL-2.0+
11 # Refer doc/README.kwbimage for more details about how-to configure
23 # Configure RGMII-0 interface pad voltage to 1.8V
28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
29 # bit23-14: zero
32 # bit29-26: zero
33 # bit31-30: 01
36 # bit 4: 0=addr/cmd in smame cycle
38 # bit 6: 0=use recommended falling edge of clk for addr/cmd
[all …]
/openbmc/linux/sound/firewire/
H A Damdtp-stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
12 #include <linux/firewire-constants.h>
17 #include "amdtp-stream.h"
27 #include "amdtp-stream-trace.h"
83 * amdtp_stream_init - initialize an AMDTP stream structure
87 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
99 return -EINVAL; in amdtp_stream_init()
101 s->protocol = kzalloc(protocol_size, GFP_KERNEL); in amdtp_stream_init()
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
13 # bit 3-0: MPPSel0 2, NF_IO[2]
14 # bit 7-4: MPPSel1 2, NF_IO[3]
15 # bit 12-8: MPPSel2 2, NF_IO[4]
16 # bit 15-12: MPPSel3 2, NF_IO[5]
17 # bit 19-16: MPPSel4 1, NF_IO[6]
18 # bit 23-20: MPPSel5 1, NF_IO[7]
19 # bit 27-24: MPPSel6 1, SYSRST_O
20 # bit 31-28: MPPSel7 0, GPO[7]
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dcore_cia.c1 // SPDX-License-Identifier: GPL-2.0
34 * NOTE: Herein lie back-to-back mb instructions. They are magic.
57 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
69 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
81 * The function number selects which function of a multi-function device
93 u8 bus = bus_dev->number; in mk_conf_addr()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
32 # bit 4: 0=addr/cmd in smame cycle
34 # bit 6: 0=use recommended falling edge of clk for addr/cmd
[all …]
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
31 # bit29-26: zero
32 # bit31-30: 01
35 # bit 4: 0=addr/cmd in smame cycle
37 # bit 6: 0=use recommended falling edge of clk for addr/cmd
[all …]

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