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/openbmc/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
73 UCH4 in3 temp6 +5V
80 ------------------
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
38 # bit4: 0, addr/cmd in same cycle
41 # bit11-7: 0 required
[all …]
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
/openbmc/linux/drivers/ata/
H A Dlibata-pata-timings.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
22 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
40 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 5, 150, 0 },
41 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 },
42 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 },
[all …]
/openbmc/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
28 .align 5
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
43 .align 5
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
[all …]
H A Dev6-memchr.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memchr.S
5 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
9 * - memory accessed as aligned quadwords only
10 * - uses cmpbge to compare 8 bytes in parallel
11 * - does binary search to find 0 byte in last
18 * - only minimum number of quadwords may be accessed
19 * - the third argument is an unsigned long
24 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
26 * E - either cluster
[all …]
H A Dev6-copy_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
13 -----------------------------
24 that the processor can fetch at most 4 aligned instructions per cycle.
28 9 cycles but I was not able to get it to run that fast -- the initial
34 -------------------------------------
45 --------------------------------------
51 forced me to add another cycle to the inner-most kernel - up to 11
53 further by unrolling the loop and doing multiple prefetches per cycle.
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
[all …]
/openbmc/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
39 #define RZ_MTU3_TMDR1 5
50 /* 8-bit MTU5 register offset macros */
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * STATIC_TRAINING - Set only if static parameters for training are set and
27 /*5 */
47 /*5 */
56 /*center DQS on read cycle */
80 /*5 */
100 /*5 */
120 /*5 */
129 /*center DQS on read cycle */
153 /*5 2 4 5 */
[all …]
/openbmc/linux/drivers/pcmcia/
H A Dsoc_common.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
64 * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
67 * minimum value of 150ns for a 250ns cycle time (for 5V operation;
68 * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
70 * has a maximum value of 150ns for a 300ns cycle time (for 5V
71 * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
75 * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
85 * The socket driver actually works nicely in interrupt-driven form,
94 * These signals change meaning when going from memory-only to
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/openbmc/openbmc/meta-ibm/recipes-phosphor/state/
H A Dphosphor-post-code-manager_%.bbappend1 # Set MaxBootCycleCount to 5 on IBM systems
2 EXTRA_OEMESON:append:p10bmc = "-Dmax-boot-cycle-count=5"
3 EXTRA_OEMESON:append:witherspoon-tacoma = "-Dmax-boot-cycle-count=5"
/openbmc/linux/drivers/pwm/
H A Dpwm-sl28cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
[all …]
/openbmc/u-boot/drivers/pwm/
H A DKconfig2 bool "Enable support for pulse-width modulation devices (PWM)"
5 A pulse-width modulator emits a pulse of varying width and provides
6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
18 used. It provides 5 channels which can be independently
26 programmable period and duty cycle. A 32-bit counter is used.
28 continuous/single-shot) are not supported by the driver.
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
52 programmable period and duty cycle. A 16-bit counter is used.
/openbmc/openbmc-test-automation/extended/
H A Dtest_bmc_reset_loop.robot2 Documentation Power cycle loop. This is to test where network service
3 ... becomes unavailable during AC-Cycle stress test.
22 ${ERROR_REGEX} SEGV|core-dump|FAILURE|Failed to start|Found ordering cycle
26 Run Multiple Power Cycle
34 Repeat Keyword ${LOOP_COUNT} times Power Cycle System Via PDU
44 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Cycle
54 Repeat Keyword ${LOOP_COUNT} times BMC Reboot Cycle
64 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Runtime Cycle
68 Power Cycle System Via PDU
69 [Documentation] Power cycle system and wait for BMC to reach Ready state.
[all …]
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg2 # Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
9 # SPDX-License-Identifier: GPL-2.0+
11 # Refer doc/README.kwbimage for more details about how-to configure
23 # Configure RGMII-0 interface pad voltage to 1.8V
26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
29 # bit23-14: zero
32 # bit29-26: zero
33 # bit31-30: 01
36 # bit 4: 0=addr/cmd in smame cycle
[all …]
/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/
H A Dampere_fanctrl.sh4 fan_hwmon_num_8_20=$(ls /sys/bus/i2c/drivers/max31790/8-0020/hwmon)
5 fan_hwmon_num_8_2f=$(ls /sys/bus/i2c/drivers/max31790/8-002f/hwmon)
8 phosphor_fan_service=("phosphor-fan-control@0.service"
9 "phosphor-fan-monitor@0.service"
10 "phosphor-fan-presence-tach@0.service")
12 declare -A fan_id_list
13 fan_list=(0 1 2 3 4 5)
14 fan_id_list=([0]=0 [1]=1 [2]=2 [3]=3 [4]=4 [5]=5)
31 systemctl daemon-reload
40 systemctl daemon-reload
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dcore_cia.c1 // SPDX-License-Identifier: GPL-2.0
34 * NOTE: Herein lie back-to-back mb instructions. They are magic.
57 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
69 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
76 * 15:11 Device number (5 bits)
81 * The function number selects which function of a multi-function device
[all …]
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
32 # bit 4: 0=addr/cmd in smame cycle
[all …]
H A Dkwbimage-is2.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
32 # bit 4: 0=addr/cmd in smame cycle
[all …]
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
31 # bit29-26: zero
32 # bit31-30: 01
35 # bit 4: 0=addr/cmd in smame cycle
[all …]
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
32 # bit 4: 0=addr/cmd in smame cycle
[all …]

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