| /openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | other.json | 3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.",
6 "BriefDescription": "This event counts the occurrence count of the micro-operation split."
9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol…
12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old…
15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | pipeline.json | 9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
21 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty…
24 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty…
27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal…
30 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal…
33 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal…
36 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal…
[all …]
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| /openbmc/linux/include/linux/ |
| H A D | timecounter.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CYCLECOUNTER_MASK(bits) (u64)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)
17 * struct cyclecounter - hardware abstraction for a free running counter
18 * Provides completely state-free accessors to the underlying hardware.
19 * Depending on which hardware it reads, the cycle counter may wrap
23 * @read: returns the current cycle value
27 * @mult: cycle to nanosecond multiplier
28 * @shift: cycle to nanosecond divisor (power of two)
38 * struct timecounter - layer above a %struct cyclecounter which counts nanoseconds
40 * cycle counter wrap around. Initialize with
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | pipeline.json | 21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
33 "PublicDescription": "No operation issued due to the frontend, pre-decode error",
36 "BriefDescription": "No operation issued due to the frontend, pre-decode error"
39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of…
42 …No operation issued due to the backend interlock. This event counts every cycle where the issue of…
45 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of…
48 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of…
[all …]
|
| /openbmc/linux/drivers/staging/vme_user/ |
| H A D | vme_fake.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
49 u32 cycle; member
57 u32 cycle; member
99 bridge = fake_bridge->driver_priv; in fake_VIRQ_tasklet()
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
132 bridge = fake_bridge->driver_priv; in fake_irq_generate()
134 mutex_lock(&bridge->vme_int); in fake_irq_generate()
136 bridge->int_level = level; in fake_irq_generate()
138 bridge->int_statid = statid; in fake_irq_generate()
144 tasklet_schedule(&bridge->int_tasklet); in fake_irq_generate()
[all …]
|
| H A D | vme_tsi148.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
80 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
84 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
102 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
122 bridge = tsi148_bridge->driver_priv; in tsi148_MB_irqhandler()
126 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
127 dev_err(tsi148_bridge->parent, "VME Mailbox %d received: 0x%x\n", in tsi148_MB_irqhandler()
143 bridge = tsi148_bridge->driver_priv; in tsi148_PERR_irqhandler()
[all …]
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/Boot/ |
| H A D | PostCode.interface.yaml | 2 Monitor Post code coming and buffer all of them based on boot cycle into
6 - name: CurrentBootCycleCount
11 - name: MaxBootCycleNum
18 - name: GetPostCodesWithTimeStamp
20 Method to get the cached post codes of the indicated boot cycle with
23 - name: Index
26 Index indicates which boot cycle of post codes is requested. 1
27 is for the most recent boot cycle. CurrentBootCycleCount is for
28 the oldest boot cycle.
30 - name: Codes
[all …]
|
| /openbmc/openbmc-test-automation/extended/ |
| H A D | test_bmc_reset_loop.robot | 2 Documentation Power cycle loop. This is to test where network service
3 ... becomes unavailable during AC-Cycle stress test.
22 ${ERROR_REGEX} SEGV|core-dump|FAILURE|Failed to start|Found ordering cycle
26 Run Multiple Power Cycle
34 Repeat Keyword ${LOOP_COUNT} times Power Cycle System Via PDU
44 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Cycle
54 Repeat Keyword ${LOOP_COUNT} times BMC Reboot Cycle
64 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Runtime Cycle
68 Power Cycle System Via PDU
69 [Documentation] Power cycle system and wait for BMC to reach Ready state.
[all …]
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| /openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 3 # shellcheck source=meta-facebook/meta-minerva/recipes-minerva/plat-tool/files/minerva-common-funct…
4 source /usr/libexec/minerva-common-functions
6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle
8 cmm-hsc-power-cycle() {
13 …# RBT_DL 100 Configures Auto-Reboot turn-on Delay (tDL(RBT)) after the REBOOT bit is set to 1
23 ret1=$(i2cset -y -f 0 0x44 0xfd 0x00)
24 ret2=$(i2cset -y -f 0 0x44 0xfd 0x0b)
27 ret3=$(i2cset -f -y 0 0x43 0xec)
29 if [ "$ret3" -ne 0 ] && { [ "$ret1" -ne 0 ] || [ "$ret2" -ne 0 ]; }; then
37 compute-blade-hsc-power-control() {
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | floating-point.json | 6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
64 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 3 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
4 source /usr/libexec/phosphor-state-manager/power-cmd
6 #Sled cycle
[all...] |
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
|
| /openbmc/linux/scripts/ |
| H A D | headerdep.pl | 2 # SPDX-License-Identifier: GPL-2.0
46 print " --all\n";
47 print " --graph\n";
49 print " -I includedir\n";
52 print " $0 --graph include/linux/kernel.h | dot -Tpng -o graph.png\n";
78 return $filename if -f $filename;
82 return $path if -f $path;
114 # $cycle[n] includes $cycle[n + 1];
115 # $cycle[-1] will be the culprit
116 my $cycle = shift;
[all …]
|
| /openbmc/linux/drivers/ata/ |
| H A D | libata-pata-timings.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
15 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
19 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
57 #define ENOUGH(v, unit) (((v)-1)/(unit)+1)
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
65 q->rec8b = EZ(t->rec8b, T); in ata_timing_quantize()
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/ |
| H A D | chassis-powercycle | 6 # shellcheck source=meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/powe…
7 source /usr/libexec/phosphor-state-manager/power-cmd
8 # shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common…
9 source /usr/libexec/yosemite4-common-functions
14 IO_EXP_SLOT_PWR_STATUS=$((CHASSIS_ID - 1))
21 if [ -z "$MANAGEMENT_BOARD_VERSION" ]; then
22 echo "Failed to check management board fru info, sled cycle keep default setting"
25 GPIOCHIP_IO_EXP_SLOT_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$SPIDER_BOARD_IO_EXP_BUS_NUM-00$IO_E…
26 GPIOCHIP_IO_EXP_SLED_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$MANAGEMENT_BOARD_IO_EXP_BUS_NUM-00$…
27 #GPIOCHIP_IO_EXP_BIC_PWR_CTRL=$(basename "/sys/bus/i2c/devices/$IO_EXP_SLOT_PWR_STATUS-00$IO_EXP_BI…
[all …]
|
| /openbmc/linux/arch/alpha/lib/ |
| H A D | ev6-csum_ipv6_magic.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
|
| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/chassis/obmc-phosphor-buttons/ |
| H A D | gpio_defs.json | 7 "multi-action": [
10 "action": "chassis-on"
14 "action": "chassis-cycle"
18 "action": "chassis-off"
26 "multi-action": [
29 "action": "chassis-on"
33 "action": "chassis-cycle"
37 "action": "chassis-off"
45 "multi-action": [
48 "action": "chassis-on"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
|
| /openbmc/openbmc/meta-fii/meta-kudo/recipes-kudo/hotswap-power-cycle/ |
| H A D | hotswap-power-cycle.bb | 1 SUMMARY = "Power Cycle by Hotswap Controller"
2 DESCRIPTION = "Power Cycle by Hotswap Controller Daemon"
4 LICENSE = "Apache-2.0"
5 LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/Apache-2.0;md5=89aea4e17d99a7cacd…
13 SRC_URI += " file://hotswap-power-cycle.service"
16 install -d ${D}${systemd_unitdir}/system/
17 …install -m 0644 ${UNPACKDIR}/hotswap-power-cycle.service ${D}${systemd_unitdir}/system/hotswap-pow…
21 SYSTEMD_SERVICE:${PN} = " hotswap-power-cycle.service"
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | floating-point.json | 44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
47 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
55 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
60 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
63 … "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
68 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issue…
71 …PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issue…
76 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB…
98 … assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | floating-point.json | 44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
47 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
55 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
60 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issue…
63 … "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
68 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issue…
71 …PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issue…
76 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB…
98 … assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
[all …]
|
| /openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/actions/ |
| H A D | gate.json | 4 "name": "Add gate action with priority and sched-entry",
17 … "cmdUnderTest": "$TC action add action gate priority 1 sched-entry close 100000000ns index 100",
20 "matchPattern": "action order [0-9]*: .*priority 1.*index 100 ref",
28 "name": "Add gate action with base-time",
41 …"cmdUnderTest": "$TC action add action gate base-time 200000000000ns sched-entry close 100000000ns…
44 "matchPattern": "action order [0-9]*: .*base-time 200s.*index 10 ref",
52 "name": "Add gate action with cycle-time",
65 …"cmdUnderTest": "$TC action add action gate cycle-time 200000000000ns sched-entry close 100000000n…
68 "matchPattern": "action order [0-9]*: .*cycle-time 200s.*index 1000 ref",
76 "name": "Add gate action with cycle-time-ext",
[all …]
|
| /openbmc/linux/drivers/pwm/ |
| H A D | pwm-sl28cpld.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
30 * - The duty cycle will switch immediately and not after a complete cycle.
31 * - Depending on the actual implementation, disabling the PWM might have
[all …]
|
| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | alibaba_pmu.rst | 2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
[all …]
|
| /openbmc/linux/drivers/net/dsa/sja1105/ |
| H A D | sja1105_tas.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0)
19 struct sja1105_tas_data *tas_data = &priv->tas_data; in sja1105_tas_set_runtime_params()
20 struct sja1105_gating_config *gating_cfg = &tas_data->gating_cfg; in sja1105_tas_set_runtime_params()
21 struct dsa_switch *ds = priv->ds; in sja1105_tas_set_runtime_params()
28 tas_data->enabled = false; in sja1105_tas_set_runtime_params()
30 for (port = 0; port < ds->num_ports; port++) { in sja1105_tas_set_runtime_params()
33 offload = tas_data->offload[port]; in sja1105_tas_set_runtime_params()
37 tas_data->enabled = true; in sja1105_tas_set_runtime_params()
39 if (max_cycle_time < offload->cycle_time) in sja1105_tas_set_runtime_params()
[all …]
|