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Searched full:cpu_ctrl (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/arch/arm/mach-berlin/
H A Dplatsmp.c31 static void __iomem *cpu_ctrl; variable
37 val = readl(cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu()
39 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu()
41 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu()
46 if (!cpu_ctrl) in berlin_boot_secondary()
71 cpu_ctrl = of_iomap(np, 0); in berlin_smp_prepare_cpus()
73 if (!cpu_ctrl) in berlin_smp_prepare_cpus()
111 val = readl(cpu_ctrl + CPU_RESET_NON_SC); in berlin_cpu_kill()
113 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_cpu_kill()
/openbmc/linux/drivers/power/reset/
H A Docelot-reset.c27 struct regmap *cpu_ctrl; member
51 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in ocelot_restart_handle()
56 regmap_update_bits(ctx->cpu_ctrl, in ocelot_restart_handle()
85 ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon); in ocelot_reset_probe()
86 if (IS_ERR(ctx->cpu_ctrl)) { in ocelot_reset_probe()
88 return PTR_ERR(ctx->cpu_ctrl); in ocelot_reset_probe()
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-sparx5.c41 struct regmap *cpu_ctrl; member
83 regmap_update_bits(sdhci_sparx5->cpu_ctrl, in sparx5_set_cacheable()
95 regmap_update_bits(sdhci_sparx5->cpu_ctrl, in sparx5_set_delay()
204 sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon); in sdhci_sparx5_probe()
205 if (IS_ERR(sdhci_sparx5->cpu_ctrl)) { in sdhci_sparx5_probe()
207 ret = PTR_ERR(sdhci_sparx5->cpu_ctrl); in sdhci_sparx5_probe()
/openbmc/linux/drivers/reset/
H A Dreset-microchip-sparx5.c25 struct regmap *cpu_ctrl; member
42 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
116 err = mchp_sparx5_map_syscon(pdev, "cpu-syscon", &ctx->cpu_ctrl); in mchp_sparx5_reset_probe()
/openbmc/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c198 u32 cpu_ctrl; in wl1251_boot_set_ecpu_ctrl() local
201 cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); in wl1251_boot_set_ecpu_ctrl()
204 cpu_ctrl &= ~flag; in wl1251_boot_set_ecpu_ctrl()
205 wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); in wl1251_boot_set_ecpu_ctrl()
/openbmc/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) macro
/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dboot.c23 u32 cpu_ctrl; in wl1271_boot_set_ecpu_ctrl() local
27 ret = wlcore_read_reg(wl, REG_ECPU_CONTROL, &cpu_ctrl); in wl1271_boot_set_ecpu_ctrl()
32 cpu_ctrl |= flag; in wl1271_boot_set_ecpu_ctrl()
33 ret = wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl); in wl1271_boot_set_ecpu_ctrl()
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dmicrochip,rst.yaml58 cpu-syscon = <&cpu_ctrl>;
/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_37xx.c361 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qrenqn_check()
372 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qacceptn_check()
383 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qdeny_check()
439 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
442 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
H A Divpu_hw_40xx.c336 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qrenqn_check()
347 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qacceptn_check()
358 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qdeny_check()
444 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
447 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Dluton.dtsi54 cpu_ctrl: syscon@10000000 { label
H A Dserval.dtsi57 cpu_ctrl: syscon@70000000 { label
H A Djaguar2.dtsi58 cpu_ctrl: syscon@70000000 { label
H A Docelot.dtsi54 cpu_ctrl: syscon@0 { label
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,serval.dtsi60 cpu_ctrl: syscon@0 { label
H A Dmscc,servalt.dtsi60 cpu_ctrl: syscon@0 { label
H A Dmscc,jr2.dtsi54 cpu_ctrl: syscon@0 { label
H A Dmscc,ocelot.dtsi60 cpu_ctrl: syscon@0 { label
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi124 cpu_ctrl: syscon@600000000 { label
145 cpu-syscon = <&cpu_ctrl>;
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x.dtsi472 cpu_ctrl: syscon@e00c0000 { label
512 cpu-syscon = <&cpu_ctrl>;
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c443 /* Toggle the POR_EN bit in CONFIG.CPU_CTRL */ in netcp_xgbe_reset_serdes()
/openbmc/linux/drivers/clk/meson/
H A Da1-peripherals.c1867 static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10);
1931 [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
2089 &cpu_ctrl,