/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sdm632.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 7 thermal-zones { 8 /delete-node/cpu1-thermal; 9 /delete-node/cpu2-thermal; 10 /delete-node/cpu3-thermal; 12 cpu0-thermal { 13 thermal-sensors = <&tsens0 13>; 15 cooling-maps { 17 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 25 cpu4-thermal { [all …]
|
H A D | ipq9574.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 9 #include <dt-bindings/clock/qcom,apss-ipq.h> 10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; [all …]
|
/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5422-odroidhc1.dts | 1 // SPDX-License-Identifier: GPL-2.0 10 /dts-v1/; 11 #include <dt-bindings/leds/common.h> 12 #include "exynos5422-odroid-core.dtsi" 16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ 19 led-controller { 20 compatible = "pwm-leds"; 22 led-1 { 26 pwm-names = "pwm2"; 27 max-brightness = <255>; [all …]
|
H A D | exynos5422-odroidxu3-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source 12 #include <dt-bindings/input/input.h> 13 #include "exynos5422-odroid-core.dtsi" 20 gpio-keys { 21 compatible = "gpio-keys"; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&power_key>; 25 power-key { 36 debounce-interval = <0>; [all …]
|
H A D | exynos5410.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <dt-bindings/clock/exynos5410.h> 15 #include <dt-bindings/clock/exynos-audss-clk.h> 16 #include <dt-bindings/interrupt-controller/arm-gic.h> 20 interrupt-parent = <&gic>; 30 #address-cells = <1>; 31 #size-cells = <0>; 33 cpu0: cpu@0 { label 35 compatible = "arm,cortex-a15"; 37 clock-frequency = <1600000000>; [all …]
|
H A D | exynos4412-prime.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 * non-Prime version. Therefore we need to update OPPs table and 12 * thermal maps accordingly. 16 /delete-property/turbo-mode; 20 opp-1600000000 { 21 opp-hz = /bits/ 64 <1600000000>; 22 opp-microvolt = <1350000>; 23 clock-latency-ns = <200000>; 25 opp-1704000000 { 26 opp-hz = /bits/ 64 <1704000000>; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/thermal/ |
H A D | thermal-cooling-devices.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 4 --- 5 $id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Thermal cooling device 11 - Amit Kucheria <amitk@kernel.org> 14 Thermal management is achieved in devicetree by describing the sensor hardware 15 and the software abstraction of cooling devices and thermal zones required to 16 take appropriate action to mitigate thermal overload. 18 The following node types are used to completely describe a thermal management [all …]
|
H A D | thermal-zones.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 4 --- 5 $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml# 6 $schema: http://devicetree.org/meta-schemas/base.yaml# 8 title: Thermal zone 11 - Amit Kucheria <amitk@kernel.org> 14 Thermal management is achieved in devicetree by describing the sensor hardware 15 and the software abstraction of cooling devices and thermal zones required to 16 take appropriate action to mitigate thermal overloads. 18 The following node types are used to completely describe a thermal management [all …]
|
H A D | mediatek,lvts-thermal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) 10 - Balsam CHIHI <bchihi@baylibre.com> 13 LVTS is a thermal management architecture composed of three subsystems, 14 a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), 15 a Converter - Low Voltage Thermal Sensor converter (LVTS), and 21 - mediatek,mt8192-lvts-ap [all …]
|
/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3288-thermal.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for RK3288 SoC thermal 8 #include <dt-bindings/thermal/thermal.h> 11 polling-delay-passive = <1000>; /* milliseconds */ 12 polling-delay = <5000>; /* milliseconds */ 15 thermal-sensors = <&tsadc 0>; 20 polling-delay-passive = <100>; /* milliseconds */ 21 polling-delay = <5000>; /* milliseconds */ 24 thermal-sensors = <&tsadc 1>; 45 cooling-maps { [all …]
|
H A D | sun5i-a13.dtsi | 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * This file is dual-licensed: you can use it either under the terms 49 #include <dt-bindings/thermal/thermal.h> 52 interrupt-parent = <&intc>; 54 thermal-zones { 57 polling-delay-passive = <250>; 58 polling-delay = <1000>; 59 thermal-sensors = <&rtp>; 61 cooling-maps { 64 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; [all …]
|
H A D | omap4-cpu-thermal.dtsi | 2 * Device Tree Source for OMAP4/5 SoC CPU thermal 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 12 #include <dt-bindings/thermal/thermal.h> 15 polling-delay-passive = <250>; /* milliseconds */ 16 polling-delay = <1000>; /* milliseconds */ 19 thermal-sensors = <&bandgap 0>; 34 cpu_cooling_maps: cooling-maps { 37 cooling-device = 38 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
/openbmc/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/thermal.h> 11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <2>; 25 compatible = "arm,psci-0.2"; 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; [all …]
|
H A D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 18 cpu0: cpu@0 { label 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; [all …]
|
/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos5433-tmu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device tree sources for Exynos5433 thermal zone 8 #include <dt-bindings/thermal/thermal.h> 11 thermal-zones { 12 atlas0_thermal: atlas0-thermal { 13 thermal-sensors = <&tmu_atlas0>; 14 polling-delay-passive = <0>; 15 polling-delay = <0>; 17 atlas0_alert_0: atlas0-alert-0 { 22 atlas0_alert_1: atlas0-alert-1 { [all …]
|
/openbmc/linux/drivers/soc/tegra/fuse/ |
H A D | fuse-tegra30.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. 11 #include <linux/nvmem-consumer.h> 12 #include <linux/nvmem-provider.h> 44 if (WARN_ON(!fuse->base)) in tegra30_fuse_read_early() 47 return readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read_early() 55 err = pm_runtime_resume_and_get(fuse->dev); in tegra30_fuse_read() 59 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); in tegra30_fuse_read() 61 pm_runtime_put(fuse->dev); in tegra30_fuse_read() 90 fuse->read_early = tegra30_fuse_read_early; in tegra30_fuse_init() [all …]
|
/openbmc/linux/tools/power/x86/turbostat/ |
H A D | turbostat.8 | 3 turbostat \- Report processor frequency and idle statistics 12 .RB [ "\--interval seconds" ] 15 idle power-state statistics, temperature and power on X86 processors. 19 in one-shot upon its completion. 22 The 5-second interval can be changed using the --interval option. 26 Options can be specified with a single or double '-', and only as much of the option 27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv… 29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri… 41 MSRs are read as 64-bits, u32 truncates the displayed value to 32-bits. 51 Any string that does not match a key-word above is used [all …]
|
/openbmc/linux/arch/arm64/boot/dts/allwinner/ |
H A D | sun50i-h5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 #include <arm/allwinner/sunxi-h3-h5.dtsi> 6 #include <dt-bindings/thermal/thermal.h> 10 #address-cells = <1>; 11 #size-cells = <0>; 13 cpu0: cpu@0 { label 14 compatible = "arm,cortex-a53"; 17 enable-method = "psci"; 19 clock-latency-ns = <244144>; /* 8 32k periods */ 20 #cooling-cells = <2>; [all …]
|
/openbmc/linux/arch/arm/boot/dts/allwinner/ |
H A D | sun5i-a13.dtsi | 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * This file is dual-licensed: you can use it either under the terms 47 #include <dt-bindings/thermal/thermal.h> 50 thermal-zones { 51 cpu-thermal { 53 polling-delay-passive = <250>; 54 polling-delay = <1000>; 55 thermal-sensors = <&rtp>; 57 cooling-maps { 60 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; [all …]
|
H A D | sun8i-h3.dtsi | 4 * This file is dual-licensed: you can use it either under the terms 43 #include "sunxi-h3-h5.dtsi" 44 #include <dt-bindings/thermal/thermal.h> 47 cpu0_opp_table: opp-table-cpu { 48 compatible = "operating-points-v2"; 49 opp-shared; 51 opp-648000000 { 52 opp-hz = /bits/ 64 <648000000>; 53 opp-microvolt = <1040000 1040000 1300000>; 54 clock-latency-ns = <244144>; /* 8 32k periods */ [all …]
|
/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap4-cpu-thermal.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for OMAP4/5 SoC CPU thermal 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 9 #include <dt-bindings/thermal/thermal.h> 12 polling-delay-passive = <250>; /* milliseconds */ 13 polling-delay = <1000>; /* milliseconds */ 19 thermal-sensors = <&bandgap 0>; 34 cpu_cooling_maps: cooling-maps { 37 cooling-device = 38 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
H A D | omap443x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 12 cpu0: cpu@0 { label 13 /* OMAP443x variants OPP50-OPPNT */ 14 operating-points = < 21 clock-latency = <300000>; /* From legacy driver */ 24 #cooling-cells = <2>; /* min followed by max */ 28 thermal-zones { 29 #include "omap4-cpu-thermal.dtsi" 37 compatible = "ti,omap4430-bandgap"; [all …]
|
/openbmc/u-boot/doc/device-tree-bindings/thermal/ |
H A D | rockchip-thermal.txt | 4 - compatible : "rockchip,rk3288-tsadc" 5 - reg : physical base address of the controller and length of memory mapped 7 - interrupts : The interrupt number to the cpu. The interrupt specifier format 9 - clocks : Must contain an entry for each entry in clock-names. 10 - clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for 12 - resets : Must contain an entry for each entry in reset-names. 14 - reset-names : Must include the name "tsadc-apb". 15 - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. 16 - rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. 17 - rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. [all …]
|
/openbmc/linux/arch/arm64/boot/dts/amlogic/ |
H A D | meson-axg-jethome-jethub-j1xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 10 /dts-v1/; 12 #include "meson-axg.dtsi" 13 #include <dt-bindings/input/input.h> 14 #include <dt-bindings/thermal/thermal.h> 24 stdout-path = "serial0:115200n8"; 27 reserved-memory { 33 emmc_pwrseq: emmc-pwrseq { 34 compatible = "mmc-pwrseq-emmc"; 35 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; [all …]
|
/openbmc/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 17 cpu = <&cpu0>; 36 cpu0: cpu@0 { label 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; [all …]
|