| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | renesas,cmt.yaml | 28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
41 - renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6
42 - renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H
43 - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
44 - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
45 - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
46 - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C
47 - renesas,r8a7790-cmt0 # 32-bit CMT0 on R-Car H2
48 - renesas,r8a7791-cmt0 # 32-bit CMT0 on R-Car M2-W
[all …]
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| /openbmc/linux/arch/sh/kernel/cpu/sh2/ |
| H A D | setup-sh7619.c | 22 WDT, EDMAC, CMT0, CMT1, enumerator
35 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
51 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
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| /openbmc/linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | setup-sh7206.c | 30 CMT0, CMT1, BSC, WDT, enumerator
60 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
112 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
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| H A D | setup-sh7203.c | 22 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
62 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
143 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
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| H A D | setup-sh7269.c | 26 USB, VDC4, CMT0, CMT1, BSC, WDT, enumerator
88 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
219 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
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| H A D | setup-sh7264.c | 25 USB, VDC3, CMT0, CMT1, BSC, WDT, enumerator
80 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
200 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
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| /openbmc/qemu/docs/system/ |
| H A D | target-rx.rst | 14 - Compare Match Timer x 2CH (CMT0,1)
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| /openbmc/linux/arch/arm/boot/dts/renesas/ |
| H A D | r8a7745-iwg22m.dtsi | 29 &cmt0 {
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| H A D | r8a77470-iwg23s-sbc.dts | 91 &cmt0 {
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| H A D | r8a7792.dtsi | 886 cmt0: timer@ffca0000 { label
887 compatible = "renesas,r8a7792-cmt0",
888 "renesas,rcar-gen2-cmt0";
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| H A D | r8a7790-stout.dts | 212 &cmt0 {
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| H A D | iwg20d-q7-common.dtsi | 175 &cmt0 {
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| H A D | r8a77470.dtsi | 981 cmt0: timer@ffca0000 { label
982 compatible = "renesas,r8a77470-cmt0",
983 "renesas,rcar-gen2-cmt0";
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| H A D | r8a7742-iwg21d-q7.dts | 220 &cmt0 {
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| /openbmc/linux/drivers/clocksource/ |
| H A D | sh_cmt.c | 55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
995 .compatible = "renesas,rcar-gen2-cmt0",
1003 .compatible = "renesas,rcar-gen3-cmt0",
1011 .compatible = "renesas,rcar-gen4-cmt0",
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | r8a7790-stout.dts | 195 &cmt0 {
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | r8a7792-cpg-mssr.c | 87 DEF_MOD("cmt0", 124, R8A7792_CLK_R),
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| H A D | r8a77470-cpg-mssr.c | 86 DEF_MOD("cmt0", 124, R8A77470_CLK_R),
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| H A D | r8a77995-cpg-mssr.c | 143 DEF_MOD("cmt0", 303, R8A77995_CLK_R),
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| H A D | r8a779f0-cpg-mssr.c | 160 DEF_MOD("cmt0", 910, R8A779F0_CLK_R),
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| H A D | r8a77970-cpg-mssr.c | 131 DEF_MOD("cmt0", 303, R8A77970_CLK_R),
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| H A D | r8a7745-cpg-mssr.c | 90 DEF_MOD("cmt0", 124, R8A7745_CLK_R),
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| H A D | r8a7794-cpg-mssr.c | 97 DEF_MOD("cmt0", 124, R8A7794_CLK_R),
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| /openbmc/u-boot/drivers/clk/renesas/ |
| H A D | r8a7792-cpg-mssr.c | 89 DEF_MOD("cmt0", 124, R8A7792_CLK_R),
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| H A D | r8a77995-cpg-mssr.c | 120 DEF_MOD("cmt0", 303, R8A77995_CLK_R),
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