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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sc7280-lpasscorecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core and audio clock control module provides the clocks and
17 include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
18 include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
23 clock-names: true
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H A Dqcom,gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm graphics clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,gpucc-sdm845.h
18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19 include/dt-bindings/clock/qcom,gpucc-sc7180.h
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H A Dmaxim,max77686.txt1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
12 dt-bindings/clock/maxim,max77686.h.
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
17 dt-bindings/clock/maxim,max77802.h.
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H A Dartpec6.txt1 * Clock bindings for Axis ARTPEC-6 chip
3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 ----------------
9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference clock (optional).
14 Main clock controller
15 ---------------------
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H A Dqcom,sc7180-lpasscorecc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm LPASS Core Clock Controller on SC7180
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm LPASS core clock control module provides the clocks and power
16 See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
21 - qcom,sc7180-lpasshm
22 - qcom,sc7180-lpasscorecc
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H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
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H A Dst,stm32mp1-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32MP1 Reset Clock Controller
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
13 The RCC IP is both a reset and a clock controller.
17 This binding uses common clock bindings
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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H A Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
6 This binding uses the following bindings:
7 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 Documentation/devicetree/bindings/reset/reset.txt
12 - compatible: should be one of the following.
13 - "hisilicon,hi3516cv300-crg"
14 - "hisilicon,hi3516cv300-sysctrl"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
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H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
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H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
10 - Jonathan Marek <jonathan@marek.ca>
13 Qualcomm display clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
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H A Dsilabs,si514.txt1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
H A Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm graphics clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,sm8450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8550-gpucc.h
19 include/dt-bindings/reset/qcom,sm8450-gpucc.h
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H A Dsilabs,si544.txt1 Binding for Silicon Labs 544 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
12 - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
14 - reg: I2C device address.
15 - #clock-cells: From common clock bindings: Shall be 0.
18 - clock-output-names: From common clock bindings. Recommended to be "si544".
21 si544: clock-controller@55 {
23 #clock-cells = <0>;
H A Drenesas,rzg2l-cpg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15 similar, but does not have Clock Monitor Registers.
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
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H A Dmicrochip,pic32.txt1 Microchip PIC32 Clock Controller Binding
2 ----------------------------------------
3 Microchip clock controller is consists of few oscillators, PLL, multiplexer
6 This binding uses common clock bindings.
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
19 rootclk: clock-controller@1f801200 {
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
27 System controller Advanced Power Bus (APB) interface clock source.
29 clock-names:
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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H A Dcomposite.txt1 Binding for TI composite clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped composite clock with multiple different sub-types;
8 a multiplexer clock with multiple input clock signals or parents, one
11 an adjustable clock rate divider, this behaves exactly as [3]
14 clock, this behaves exactly as [4]
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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/openbmc/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen.txt30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
16 - description: |
18 figure out the chip-id.
20 … - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
21 - const: qcom,adreno
22 - description: |
24 figure out the gpu-id and patch level.
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
21 - st,stm32mp15-i2c
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
4 Documentation/devicetree/bindings/mmc/mmc.txt and the properties
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
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/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sdm845-adsp-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 - qcom,sdm845-adsp-pil
28 - description: Watchdog interrupt
29 - description: Fatal interrupt
30 - description: Ready interrupt
31 - description: Handover interrupt
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip.txt1 Device Tree Clock bindings for arch-rockchip
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 These bindings are deprecated!
10 Please use the soc specific CRU bindings instead.
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
20 - reg : shall be the control register address(es) for the clock.
21 - #clock-cells : from common clock binding; shall be set to 1
22 - clock-output-names : the corresponding gate names that the clock controls
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