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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dsyna,rmi4.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jason A. Donenfeld <Jason@zx2c4.com>
11 - Matthias Schiffer <matthias.schiffer@ew.tq-group.com
12 - Vincent Huang <vincent.huang@tw.synaptics.com>
22 - syna,rmi4-i2c
23 - syna,rmi4-spi
28 '#address-cells':
31 '#size-cells':
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/openbmc/linux/drivers/input/rmi4/
H A Drmi_2d_sensor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2016 Synaptics Incorporated
16 #define RMI_2D_REL_POS_MIN -128
26 struct rmi_2d_axis_alignment *axis_align = &sensor->axis_align; in rmi_2d_sensor_abs_process()
29 if (obj->type == RMI_2D_OBJECT_NONE) in rmi_2d_sensor_abs_process()
32 if (axis_align->flip_x) in rmi_2d_sensor_abs_process()
33 obj->x = sensor->max_x - obj->x; in rmi_2d_sensor_abs_process()
35 if (axis_align->flip_y) in rmi_2d_sensor_abs_process()
36 obj->y = sensor->max_y - obj->y; in rmi_2d_sensor_abs_process()
38 if (axis_align->swap_axes) in rmi_2d_sensor_abs_process()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
15 #define REG_MASK(n) ((BIT(n)) - 1)
35 * struct dpu_hw_blk - opaque hardware block object
46 * @ clip: clip shift
50 * @ thr_high: low threshold
53 * @ adjust_a: A-coefficients for mapping curve
54 * @ adjust_b: B-coefficients for mapping curve
55 * @ adjust_c: C-coefficients for mapping curve
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/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
26 #define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */
27 #define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
31 #define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 /delete-node/ &adsp_mem;
21 /delete-node/ &audio_mem;
22 /delete-node/ &cont_splash_mem;
23 /delete-node/ &mba_mem;
24 /delete-node/ &mpss_mem;
25 /delete-node/ &peripheral_region;
[all …]
H A Dsdm845-xiaomi-polaris.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/input/linux-event-codes.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
25 /delete-node/ &rmtfs_mem;
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/openbmc/linux/drivers/media/i2c/
H A Dov8858.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <media/media-entity.h>
23 #include <media/v4l2-async.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
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H A Dar0521.c1 // SPDX-License-Identifier: GPL-2.0
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-fwnode.h>
14 #include <media/v4l2-subdev.h>
147 return &container_of(ctrl->handler, struct ar0521_dev, in ctrl_to_sd()
148 ctrls.handler)->sd; in ctrl_to_sd()
158 return div_u64(v + d - 1, d); in div64_round_up()
163 switch (sensor->fmt.code) { in ar0521_code_to_bpp()
168 return -EINVAL; in ar0521_code_to_bpp()
[all …]
H A Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
41 #define GAIN 0x00 /* AGC - Gain control gain setting */
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_psr.c44 * Since Haswell Display controller supports Panel Self-Refresh on display
58 * The implementation uses the hardware-based PSR support which automatically
59 * enters/exits self-refresh mode. The hardware takes care of sending the
62 * changes to know when to exit self-refresh mode again. Unfortunately that
67 * issues the self-refresh re-enable code is done from a work queue, which
75 * entry/exit allows the HW to enter a low-power state even when page flipping
91 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
155 * In standby mode (as opposed to link-off) this makes no difference
169 * The rest of the bits are more self-explanatory and/or
175 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
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H A Dintel_atomic_plane.c28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
55 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); in intel_plane_state_reset()
57 plane_state->scaler_id = -1; in intel_plane_state_reset()
67 return ERR_PTR(-ENOMEM); in intel_plane_alloc()
72 return ERR_PTR(-ENOMEM); in intel_plane_alloc()
77 plane->base.state = &plane_state->uapi; in intel_plane_alloc()
84 intel_plane_destroy_state(&plane->base, plane->base.state); in intel_plane_free()
89 * intel_plane_duplicate_state - duplicate plane state
93 * Intel-specific) for the specified plane.
[all …]
/openbmc/linux/arch/arm64/mm/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2005 Russell King
23 #include <linux/dma-direct.h>
24 #include <linux/dma-map-ops.h>
38 #include <asm/kernel-pgtable.h>
47 #include <asm/xen/swiotlb-xen.h>
55 s64 memstart_addr __ro_after_init = -1;
60 * and ZONE_DMA32. By default ZONE_DMA covers the 32-bit addressable memory
61 * unless restricted on specific platforms (e.g. 30-bit on Raspberry Pi 4).
62 * In such case, ZONE_DMA32 covers the rest of the 32-bit addressable memory,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c56 struct resource_context *res_ctx = &context->res_ctx; in dce60_should_enable_fbc()
57 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce60_should_enable_fbc()
60 ASSERT(dc->fbc_compressor); in dce60_should_enable_fbc()
63 if (!dc->ctx->fbc_gpu_addr) in dce60_should_enable_fbc()
67 if (context->stream_count != 1) in dce60_should_enable_fbc()
70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
71 if (res_ctx->pipe_ctx[i].stream) { in dce60_should_enable_fbc()
73 pipe_ctx = &res_ctx->pipe_ctx[i]; in dce60_should_enable_fbc()
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
86 #define UNABLE_TO_SPLIT -1
206 init_data->num_virtual_links, dc); in dc_create_resource_pool()
210 init_data->num_virtual_links, dc); in dc_create_resource_pool()
214 init_data->num_virtual_links, dc); in dc_create_resource_pool()
219 init_data->num_virtual_links, dc); in dc_create_resource_pool()
223 init_data->num_virtual_links, dc); in dc_create_resource_pool()
227 init_data->num_virtual_links, dc); in dc_create_resource_pool()
231 init_data->num_virtual_links, dc); in dc_create_resource_pool()
235 init_data->num_virtual_link in dc_create_resource_pool()
834 shift_rec(const struct rect * rec_in,int x,int y) shift_rec() argument
[all...]
/openbmc/linux/drivers/staging/media/ipu3/include/uapi/
H A Dintel-ipu3.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
51 * @y_start: Y value of top left corner of ROI
53 * @y_end: Y value of bottom right corner of ROI
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
[all …]
/openbmc/linux/tools/power/pm-graph/
H A DREADME8 pm-graph: suspend/resume/boot timing analysis tools
11 …Home Page: https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/overvi…
13 Report bugs/issues at bugzilla.kernel.org Tools/pm-graph
14 - https://bugzilla.kernel.org/buglist.cgi?component=pm-graph&product=Tools
17 - Getting Started:
20 - Feature Summary:
21 https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/features.html
23 - upstream version in git:
24 git clone https://github.com/intel/pm-graph/
27 - Overview
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H A Dsleepgraph.py2 # SPDX-License-Identifier: GPL-2.0-only
21 # https://01.org/pm-graph
23 # git@github.com:intel/pm-graph
36 # CONFIG_DEVMEM=y
37 # CONFIG_PM_DEBUG=y
38 # CONFIG_PM_SLEEP_DEBUG=y
39 # CONFIG_FTRACE=y
40 # CONFIG_FUNCTION_TRACER=y
41 # CONFIG_FUNCTION_GRAPH_TRACER=y
42 # CONFIG_KPROBES=y
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/openbmc/u-boot/drivers/video/
H A Dstb_truetype.h1 // stb_truetype.h - v1.08 - public domain
2 // authored from 2009-2015 by Sean Barrett / RAD Game Tools
8 // render glyphs to one-channel bitmaps with antialiasing (box filter)
11 // non-MS cmaps
14 // cleartype-style AA?
16 // optimize: build edge-list directly from curves
32 // Ivan-Assen Ivanov
51 // 1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges
52 // 1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints;
54 // fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?);
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c73 * For eDP, after power-up/power/down,
83 hws->ctx
88 hws->regs->reg
92 hws->shifts->field_name, hws->masks->field_name
100 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
209 struct dc_context *ctx = dc->ctx; in dce110_enable_display_power_gating()
210 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
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/openbmc/u-boot/doc/
H A DREADME.x861 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on x86
9 This document describes the information about U-Boot running on x86 targets,
13 ------
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
26 - Bayley Bay CRB
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/openbmc/linux/drivers/net/wireless/intel/iwlegacy/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
32 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
33 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
34 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
46 #define U32_PAD(n) ((4-(n))&0x3)
48 /* CT-KILL constants */
56 * Use default noise value of -127 ... this is below the range of measurable
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/openbmc/linux/drivers/video/fbdev/
H A Datafb.c2 * linux/drivers/video/atafb.c -- Atari builtin chipset frame buffer device
11 * - 03 Jan 95: Original version by Martin Schaller: The TT driver and
13 * - 09 Jan 95: Roman: I've added the hardware abstraction (hw_switch)
16 * - 07 May 95: Martin: Added colormap operations for the external driver
17 * - 21 May 95: Martin: Added support for overscan
19 * - Jul 95: Guenther Kelleter <guenther@pool.informatik.rwth-aachen.de>:
23 * - 27 Dec 95: Guenther: Implemented user definable video modes "user[0-7]"
25 * "R<x>;<y>;<depth>". (Makes sense only on Falcon)
28 * - 23 Sep 97: Juergen: added xres_virtual for cards like ProMST
29 * The external-part is legacy, therefore hardware-specific
[all …]
H A Damifb.c2 * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device
4 * Copyright (C) 1995-2003 Geert Uytterhoeven
30 * - 24 Jul 96: Copper generates now vblank interrupt and
32 * - 14 Jul 96: Rework and hopefully last ECS bugs fixed
33 * - 7 Mar 96: Hardware sprite support by Roman Zippel
34 * - 18 Feb 96: OCS and ECS support by Roman Zippel
36 * - 2 Dec 95: AGA version by Geert Uytterhoeven
107 ---------------------
111 +----------+---------------------------------------------+----------+-------+
115 +----------###############################################----------+-------+
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/openbmc/linux/drivers/media/usb/gspca/
H A Dspca508.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 Jean-Francois Moine <http://moinejf.free.fr>
58 * Initialization data: this is the first set-up data written to the
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
79 /* --------------------------------------- */
82 /* --------------------------------------- */
91 /* READ { 0x0001, 0x8803 } -> 0000: 00 */
92 /* READ { 0x0001, 0x8802 } -> 0000: 08 */
96 /* READ { 0x0001, 0x8803 } -> 0000: 00 */
97 /* READ { 0x0001, 0x8803 } -> 0000: 00 */
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/openbmc/linux/drivers/tty/serial/
H A Dserial_core.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
43 * lockdep: port->lock is initialized in two places, but we
44 * want only one lock-class:
48 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
62 return !!(uport->status & UPSTAT_DCD_ENABLE); in uart_dcd_enabled()
67 if (atomic_add_unless(&state->refcount, 1, 0)) in uart_port_ref()
68 return state->uart_port; in uart_port_ref()
74 if (atomic_dec_and_test(&uport->state->refcount)) in uart_port_deref()
75 wake_up(&uport->state->remove_wait); in uart_port_deref()
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