/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | sifive,clint.yaml | 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml# 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 18 interrupt controller is the parent interrupt controller for CLINT device. 19 The clock frequency of CLINT is specified via "timebase-frequency" DT 23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however 32 - canaan,k210-clint # Canaan Kendryte K210 33 - sifive,fu540-c000-clint # SiFive FU540 34 - starfive,jh7100-clint # StarFive JH7100 35 - starfive,jh7110-clint # StarFive JH7110 36 - const: sifive,clint0 # SiFive CLINT v0 IP block [all …]
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/openbmc/u-boot/arch/riscv/lib/ |
H A D | sifive_clint.c | 5 * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). 6 * The CLINT block holds memory-mapped control and status registers 30 if (!gd->arch.clint) { \ 34 gd->arch.clint = ret; \ 42 *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); in riscv_get_time() 51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp() 60 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_send_ipi() 69 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_clear_ipi()
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/openbmc/linux/drivers/clocksource/ |
H A D | timer-clint.c | 6 * CLINT MMIO timer device. 9 #define pr_fmt(fmt) "clint: " fmt 28 #include <asm/clint.h> 35 /* CLINT manages IPI and Timer for RISC-V M-mode */ 172 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or in clint_timer_init_dt() 203 /* If CLINT ipi or timer irq not found then fail */ in clint_timer_init_dt() 239 "clint-timer", &clint_clock_event); in clint_timer_init_dt() 259 "clockevents/clint/timer:starting", in clint_timer_init_dt()
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H A D | Kconfig | 646 bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST 651 This option enables the CLINT timer for RISC-V systems. The CLINT
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H A D | Makefile | 83 obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
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/openbmc/u-boot/arch/riscv/include/asm/ |
H A D | syscon.h | 12 * So far only SiFive's Core Local Interruptor (CLINT) is defined. 16 RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
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H A D | global_data.h | 17 void __iomem *clint; /* clint base address */ member
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/openbmc/qemu/docs/system/riscv/ |
H A D | sifive_u.rst | 14 * Core Local Interruptor (CLINT) 53 * Should contain a node for the CLINT device with a compatible string 135 Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT 140 clint: clint@2000000 {
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H A D | virt.rst | 16 * Core Local Interruptor (CLINT) 44 * Should contain a node for the CLINT device with a compatible string 108 SiFive CLINT. When not specified, this option is assumed to be "off".
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H A D | microchip-icicle-kit.rst | 20 * Core Level Interruptor (CLINT) 45 * Should contain a node for the CLINT device with a compatible string
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H A D | shakti-c.rst | 22 * Core Level Interruptor (CLINT)
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/openbmc/linux/arch/riscv/boot/dts/starfive/ |
H A D | jh7100.dtsi | 143 clint: clint@2000000 { label 144 compatible = "starfive,jh7100-clint", "sifive,clint0";
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H A D | jh7110.dtsi | 339 clint: timer@2000000 { label 340 compatible = "starfive,jh7110-clint", "sifive,clint0";
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/openbmc/linux/arch/riscv/include/asm/ |
H A D | clint.h | 14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid
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H A D | timex.h | 15 #include <asm/clint.h>
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/openbmc/linux/arch/riscv/boot/dts/thead/ |
H A D | th1520.dtsi | 158 clint: timer@ffdc000000 { label 159 compatible = "thead,th1520-clint", "thead,c900-clint";
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/openbmc/u-boot/doc/ |
H A D | README.qemu-riscv | 13 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
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/openbmc/u-boot/arch/riscv/ |
H A D | Kconfig | 109 The SiFive CLINT block holds memory-mapped control and status registers
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/openbmc/linux/arch/riscv/boot/dts/microchip/ |
H A D | mpfs.dtsi | 199 clint: clint@2000000 { label 200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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/openbmc/qemu/hw/riscv/ |
H A D | spike.c | 10 * 1) CLINT (Timer and IPI) 160 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); in create_fdt()
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H A D | microchip_pfsoc.c | 11 * 0) CLINT (Core Level Interruptor) 64 /* CLINT timebase frequency */ 249 /* CLINT */ in microchip_pfsoc_soc_realize()
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H A D | sifive_u.c | 11 * 1) CLINT (Core Level Interruptor) 65 /* CLINT timebase frequency */ 209 nodename = g_strdup_printf("/soc/clint@%lx", in create_fdt()
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H A D | sifive_e.c | 9 * 1) CLINT (Core Level Interruptor)
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/openbmc/linux/drivers/irqchip/ |
H A D | irq-riscv-intc.c | 82 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
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/openbmc/openbmc/poky/meta/files/common-licenses/ |
H A D | SMAIL_GPL | 4 Guy Maor <maor@debian.org>, and are now maintained by Clint Adams
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