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/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
33 /* Channel Image Control Register */
98 #define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
143 /* Channel Interrupt Enable Register */
153 /* Channel Status Register */
179 /* Channel Scale Factor Register */
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
30 /* bit 8~16 for dot 11n IO types
32 * bit 10~11 bandwidth
51 /* bit 8~16 for dot 11ac IO types
53 * bit 11~13 bandwidth
73 #define BRCMU_CHSPEC_D11AC_BW_SHIFT 11
100 BRCMU_CHAN_SB_NONE = -1,
[all …]
/openbmc/openbmc/meta-bytedance/meta-g220a/recipes-phosphor/configuration/entity-manager/
H A Dg220a_baseboard.json360 "Index": 11,
595 "Index": 11,
897 11
947 "Channel": 0, number
958 "Spdpcidevice": 11,
963 "Channel": 0, number
974 "Spdpcidevice": 11,
979 "Channel": 1, number
990 "Spdpcidevice": 11,
995 "Channel": 1, number
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
73 * struct twl6030_chnl_calib - channel calibration
85 * struct twl6030_ideal_code - GPADC calibration parameters
89 * @channel: channel number
96 int channel; member
106 * struct twl6030_gpadc_platform_data - platform specific data
111 * @channel_to_reg: pointer to ADC function to convert channel to
119 int (*start_conversion)(int channel);
[all …]
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A D11h.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
14 priv->state_11h.is_11h_enabled = true; in mwifiex_init_11h_params()
15 priv->state_11h.is_11h_active = false; in mwifiex_init_11h_params()
20 return priv->state_11h.is_11h_active; in mwifiex_is_11h_active()
22 /* This function appends 11h info to a buffer while joining an
39 radio_type = mwifiex_band_to_radio_type((u8) bss_desc->bss_band); in mwifiex_11h_process_infra_join()
40 sband = priv->wdev.wiphy->bands[radio_type]; in mwifiex_11h_process_infra_join()
43 cap->header.type = cpu_to_le16(WLAN_EID_PWR_CAPABILITY); in mwifiex_11h_process_infra_join()
44 cap->header.len = cpu_to_le16(2); in mwifiex_11h_process_infra_join()
[all …]
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
52 RF_CHANNEL(11) = 0x77,
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY driver
7 Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
23 static inline u16 channel2freq_lp(u8 channel) in channel2freq_lp() argument
25 if (channel < 14) in channel2freq_lp()
26 return (2407 + 5 * channel); in channel2freq_lp()
27 else if (channel == 14) in channel2freq_lp()
29 else if (channel < 184) in channel2freq_lp()
30 return (5000 + 5 * channel); in channel2freq_lp()
32 return (4000 + 5 * channel); in channel2freq_lp()
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
38 .reset = RESET_VAL(0x0, 12, 11),
49 .channel = BCM_SR_GENPLL0_125M_CLK,
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
61 .channel = BCM_SR_GENPLL0_250M_CLK,
67 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
73 .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
51 .reset = RESET_VAL(0x0, 11, 10),
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
[all …]
H A Dclk-nsp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
38 .reset = RESET_VAL(0x0, 11, 10),
48 .channel = BCM_NSP_GENPLL_PHY_CLK,
54 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
60 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
66 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
[all …]
/openbmc/u-boot/drivers/dma/
H A DMCD_tasksInit.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
22 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainNoEu() argument
24 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainNoEu()
29 MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */ in MCD_startDmaChainNoEu()
52 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainNoEu()
60 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleNoEu() argument
62 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaSingleNoEu()
83 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleNoEu()
90 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainEu() argument
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Drf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
17 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3); in rtl8821ae_phy_rf6052_set_bandwidth()
18 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3); in rtl8821ae_phy_rf6052_set_bandwidth()
21 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1); in rtl8821ae_phy_rf6052_set_bandwidth()
22 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1); in rtl8821ae_phy_rf6052_set_bandwidth()
25 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0); in rtl8821ae_phy_rf6052_set_bandwidth()
26 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0); in rtl8821ae_phy_rf6052_set_bandwidth()
38 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_rf6052_set_cck_txpower()
48 if (rtlefuse->eeprom_regulatory != 0) in rtl8821ae_phy_rf6052_set_cck_txpower()
[all …]
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* Channel interrupts */
74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
134 #define MCDE_OVLXCR_BURSTSIZE_HW_8W 11
153 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11
164 #define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11
211 #define MCDE_OVLXCOMP_CH_ID_SHIFT 11
218 /* DPI/TV configuration registers, channel A and B */
232 /* TV blanking control register 1, channel A and B */
235 #define MCDE_TVBL1_BEL1_SHIFT 0 /* VFP vertical front porch 11 bits */
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dscan.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 * enum iwl_scan_subcmd_ids - scan commands
29 * struct iwl_ssid_ie - directed scan network information element
33 * each channel may select different ssids from among the 20 entries.
49 #define IWL_SCAN_MAX_PROFILES 11
72 * struct iwl_scan_offload_blocklist - SCAN_OFFLOAD_BLACKLIST_S
75 * @client_bitmap: clients ignore this entry - enum scan_framework_client
[all …]
H A Dnvm-reg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_regulatory_and_nvm_subcmd_ids - regulatory/NVM commands
53 * enum iwl_nvm_access_op - NVM access opcode
63 * enum iwl_nvm_access_target - target of the NVM_ACCESS_CMD
75 * enum iwl_nvm_section_type - section types for NVM_ACCESS_CMD
91 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
97 * struct iwl_nvm_access_cmd - Request the device to send an NVM section
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-minipack.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,minipack-bmc", "aspeed,ast2500";
23 * i2c switch 2-0070, pca9548, 8 child channels assigned
24 * with bus number 16-23.
36 * i2c switch 8-0070, pca9548, 8 child channels assigned
37 * with bus number 24-31.
49 * i2c switch 9-0070, pca9548, 8 child channels assigned
50 * with bus number 32-39.
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-nvm-parse.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
14 #include "iwl-drv.h"
15 #include "iwl-modparams.h"
16 #include "iwl-nvm-parse.h"
17 #include "iwl-prph.h"
18 #include "iwl-io.h"
19 #include "iwl-csr.h"
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
50 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
51 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
52 efuse->pa_type_2g = map->pa_type; in rtw8822b_read_efuse()
[all …]
/openbmc/linux/drivers/staging/rtl8192e/
H A Ddot11d.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
11 u8 channel[32]; member
16 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64,
18 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11},
19 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56,
21 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
22 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
23 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
25 {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
33 11: UART port 2
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0+ */
17 * DMA linked list structure used with a channel's LLI register;
18 * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
29 #define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */
46 #define DMAC_CHAN_FLOW_D_M2P (0x1 << 11)
47 #define DMAC_CHAN_FLOW_D_P2M (0x2 << 11)
58 /* Channel enable bit */
62 int lpc32xx_dma_start_xfer(unsigned int channel,
64 int lpc32xx_dma_wait_status(unsigned int channel);

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