| /openbmc/linux/certs/ |
| H A D | system_keyring.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <keys/asymmetric-type.h>
36 * restrict_link_by_builtin_trusted - Restrict keyring addition by built-in CA
40 * @restriction_key: A ring of keys that can be used to vouch for the new cert.
42 * Restrict the addition of keys into a keyring based on the key-to-be-added
55 * restrict_link_by_digsig_builtin - Restrict digitalSignature key additions by the built-in keyring
59 * @restriction_key: A ring of keys that can be used to vouch for the new cert.
61 * Restrict the addition of keys into a keyring based on the key-to-be-added
76 * restrict_link_by_builtin_and_secondary_trusted - Restrict keyring
77 * addition by both built-in and secondary keyrings.
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| /openbmc/qemu/docs/ |
| H A D | block-replication.txt | 2 ----------------------------------------
8 See the COPYING file in the top-level directory.
11 for COLO (COarse-grain LOck-stepping) where the Secondary VM is running.
12 It can also be applied for FT/HA (Fault-tolerance/High Assurance) scenario,
13 where the Secondary VM is not running.
19 consecutive checkpoints. The VM state of the Primary and Secondary VM is
22 the modified disk contents in the Secondary VM must be buffered, and are
25 the Primary disk are asynchronously forwarded to the Secondary node.
30 +----------------------+ +------------------------+
31 |Primary Write Requests| |Secondary Write Requests|
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|
| H A D | COLO-FT.txt | 1 COarse-grained LOck-stepping Virtual Machines for Non-stop Service
2 ----------------------------------------
8 See the COPYING file in the top-level directory.
14 application-agnostic software-implemented hardware fault tolerance,
15 also known as "non-stop service".
17 COLO (COarse-grained LOck-stepping) is a high availability solution.
18 Both primary VM (PVM) and secondary VM (SVM) run in parallel. They receive the
27 The primary node running the PVM, and the secondary node running the SVM
33 primary node, and then forwarded to the secondary node, so that both the PVM
44 Primary Node Secondary Node
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|
| /openbmc/u-boot/doc/ |
| H A D | README.arm64 | 1 U-Boot for arm64
5 The initial arm64 U-Boot port was developed before hardware was available,
7 These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
13 1. U-Boot can run at any exception level it is entered in, it is
14 recommened to enter it in EL3 if U-Boot takes some responsibilities of a
16 or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
17 that of a boot loader. It can drop to lower exception levels before
20 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
21 use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
22 is used to encode the initial addend of rela to u-boot.bin. After running,
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| H A D | README.mpc85xx-spin-table | 4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
|
| /openbmc/linux/Documentation/devicetree/bindings/net/can/ |
| H A D | st,stm32-bxcan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: STMicroelectronics BxCAN controller for CAN bus
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
25 two CAN peripherals in dual CAN configuration. In that case they share
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|
| /openbmc/linux/Documentation/arch/sparc/oradax/ |
| H A D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
39 …machine, however, internal resource limitations within the virtual machine can cause CCB submissio…
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
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| /openbmc/linux/include/linux/ |
| H A D | mmu_notifier.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 * enum mmu_notifier_event - reason for the mmu notifier callback
68 * freed. This can run concurrently with other mmu notifier
70 * should tear down all secondary mmu mappings and freeze the
71 * secondary mmu. If this method isn't implemented you've to
73 * through the secondary mmu by the time the last thread with
74 * tsk->mm == mm exits.
76 * As side note: the pages freed after ->release returns could
78 * address with a different cache model, so if ->release isn't
80 * through the secondary mmu are terminated by the time the
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-interconnect.json | 100 … "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
104 …"PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
109 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
113 … "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
118 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
122 … "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
127 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
131 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
136 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
140 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | smp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1)
14 #define CPU_MMU_OFF (-1)
16 /* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */
20 /* Fatal system error detected by secondary CPU, crash the system */
39 * the expense of. If we're preemptible, the value can be stale at use anyway.
40 * And we can't use this_cpu_ptr() either, as that winds up recursing back
70 * Called from the secondary holding pen, this is the secondary CPU entry point.
75 * Initial data for bringing up a secondary CPU.
76 * @status - Result passed back from the secondary CPU to
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|
| /openbmc/linux/Documentation/fb/ |
| H A D | matroxfb.rst | 15 * You can run XF{68,86}_FBDev or XFree86 fbdev driver on top of /dev/fb0
16 * Most important: boot logo :-)
34 box) and matroxfb (for graphics mode). You should not compile-in vesafb
35 unless you have primary display on non-Matrox VBE2.0 device (see
43 -------------
58 -------------------------
73 ----------
82 You can enter these number either hexadecimal (leading `0x`) or decimal
83 (0x100 = 256). You can also use value + 512 to achieve compatibility
86 Non-listed number can be achieved by more complicated command-line, for
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|
| H A D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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|
| /openbmc/u-boot/doc/uImage.FIT/ |
| H A D | verified-boot.txt | 1 U-Boot Verified Boot
5 ------------
11 into the boot process. An example might be loading U-Boot from read-only
12 memory, then loading a signed kernel, then using the kernel's dm-verity
15 A key point is that it is possible to field-upgrade the software on machines
18 It is also possible to add a secondary signed firmware image, in read-write
19 memory, so that firmware can easily be upgraded in a secure manner.
23 -------
25 Images are signed using a private key known only to the signer, but can
26 be verified using a public key. As its name suggests the public key can be
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|
| /openbmc/phosphor-dbus-interfaces/ |
| H A D | requirements.md | 11 Do not over-optimize properties by selecting explicit sizes such as `uint8`
17 non-countable values prefer `uint64` or `int64`.
23 as "... can be shown in user interfaces but this field should not be used for
28 The sdbusplus implementation has built-in support for enumerations, which flow
32 In some cases it is useful to have hardware-specific or OEM values for
34 the values contained within are to be sdbusplus-enumerations of a specific
35 pattern. See the [software compatibility][software-compat] and [dump
36 interface][dump-interface] as two current examples of this.
38 [software-compat]:
39 …https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/Software/…
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|
| /openbmc/linux/drivers/block/drbd/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 DRBD is a shared-nothing, synchronously replicated block device. It
21 clusters and in this context, is a "drop-in" replacement for shared
24 Each minor device has a role, which can be 'primary' or 'secondary'.
28 node with the device in 'secondary' state. The secondary device
31 DRBD can also be used in dual-Primary mode (device writable on both
32 nodes), which means it can exhibit shared disk semantics in a
33 shared-nothing cluster. Needless to say, on top of dual-Primary
38 See also: https://www.drbd.org/, http://www.linux-ha.org
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-g-tuner.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_TUNER - VIDIOC_S_TUNER - Get or set tuner attributes
52 Since this is a write-only ioctl, it does not return the actually
68 .. flat-table:: struct v4l2_tuner
69 :header-rows: 0
70 :stub-columns: 0
72 * - __u32
73 - ``index``
74 - :cspan:`1` Identifies the tuner, set by the application.
75 * - __u8
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|
| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | MPL-2.0-no-copyleft-exception | 13 1.5. "Incompatible With Secondary Licenses" means
17 …erms of version 1.1 or earlier of the License, but not also under the terms of a Secondary License.
35 …1.12. "Secondary License" means either the GNU General Public License, Version 2.0, the GNU Lesser…
44 Each Contributor hereby grants You a world-wide, royalty-free, non-exclusive license:
65 …uent version of this License (see Section 10.2) or under the terms of a Secondary License (if perm…
79 …he Covered Software is governed by the terms of this License, and how they can obtain a copy of th…
84 …ection 3.1, and You must inform recipients of the Executable Form how they can obtain a copy of su…
89 …Secondary Licenses, and the Covered Software is not Incompatible With Secondary Licenses, this Lic…
102 …-compliance by some reasonable means prior to 60 days after You have come back into compliance. Mo…
104 …infringement claim (excluding declaratory judgment actions, counter-claims, and cross-claims) alle…
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|
| /openbmc/webui-vue/docs/guide/components/buttons/ |
| H A D | index.md | 4 the `primary` and `secondary` buttons. Buttons, like all Boostrap-vue components
5 can be themed by setting the `variant` prop on the component to one of the
6 [theme-color map keys](/guide/guidelines/colors). To create a button that looks
9 [Learn more about Bootstrap-vue buttons](https://bootstrap-vue.js.org/docs/components/button)
13 Add `btn-icon-only` class to the button and add `title` attribute to get helper
22 <b-button variant="primary">Primary</b-button>
23 <b-button variant="primary">
24 <icon-add />
26 </b-button>
27 <b-button variant="secondary">Secondary</b-button>
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|
| /openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/ |
| H A D | coex.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2013-2014, 2018-2020, 2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
11 #include "iwl-modparams.h"
13 #include "iwl-debug.h"
100 * Checking that we hold mvm->mutex is a good idea, but the rate in iwl_get_coex_type()
101 * control can't acquire the mutex since it runs in Tx path. in iwl_get_coex_type()
109 chanctx_conf = rcu_dereference(vif->bss_conf.chanctx_conf); in iwl_get_coex_type()
112 chanctx_conf->def.chan->band != NL80211_BAND_2GHZ) { in iwl_get_coex_type()
119 if (mvm->cfg->bt_shared_single_ant) { in iwl_get_coex_type()
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|
| /openbmc/linux/arch/arm/mach-mvebu/ |
| H A D | coherency_ll.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * coherency fabric. This function is called by each of the secondary
12 * function have to callable from assembly. It can also be called by a
23 .arch armv7-a
55 * coherency CPU mask can be used with the coherency fabric
57 * endian-swapped as appropriate so that the calling functions do not
73 * MMU can be disabled. The Armada XP SoC has an exclusive monitor
84 * calls. This function is used very early in the secondary
109 * calls. This function is used very early in the secondary
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|
| /openbmc/linux/arch/powerpc/kexec/ |
| H A D | core_64.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005, IBM Corp.
49 for (i = 0; i < image->nr_segments; i++) in machine_kexec_prepare()
50 if (image->segment[i].mem < __pa(_end)) in machine_kexec_prepare()
51 return -ETXTBSY; in machine_kexec_prepare()
55 basep = of_get_property(node, "linux,tce-base", NULL); in machine_kexec_prepare()
56 sizep = of_get_property(node, "linux,tce-size", NULL); in machine_kexec_prepare()
63 for (i = 0; i < image->nr_segments; i++) { in machine_kexec_prepare()
64 begin = image->segment[i].mem; in machine_kexec_prepare()
65 end = begin + image->segment[i].memsz; in machine_kexec_prepare()
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|
| /openbmc/linux/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
49 Creating pci-epf-ntb Device
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|
| /openbmc/docs/designs/ |
| H A D | redfish-authorization.md | 22 operation-to-privilege mapping.
26 `ConfigureManager`, etc). A service may define custom OEM roles (read-only). A
27 service may even allow custom client-defined roles to be created, modified, and
30 The operation-to-privilege mapping is defined for every resource type and
35 official registry collection as a base operation-to-privilege mapping. It also
47 **Note**, in the Redfish spec, OEM roles can be added via POST to the
49 and properties of `Mappings` are all read-only.
53 1. https://redfish.dmtf.org/schemas/DSP0266_1.15.1.html#privilege-model
54 2. https://redfish.dmtf.org/schemas/DSP0266_1.15.1.html#redfish-service-operation-to-privilege-mapp…
58 ### Phosphor-user-manager
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| /openbmc/linux/security/integrity/ima/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 being measured, we can tell.
26 TPM hardware, so that the TPM can prove to a third party
43 Depending on the IMA policy, the measurement list can grow to
70 limited to 255 characters. The 'ima-ng' measurement list
72 pathnames. The configured default template can be replaced
76 bool "ima-ng (default)"
78 bool "ima-sig"
83 default "ima-ng" if IMA_NG_TEMPLATE
84 default "ima-sig" if IMA_SIG_TEMPLATE
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap-smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
110 * ICIALLU) to activate the workaround for secondary Core.
115 * In General Purpose(GP) devices, ACR bit settings can only be done
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA in omap4_secondary_init()
153 * OMAP443X GP devices- SMP bit isn't accessible. in omap4_secondary_init()
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|