cache\-level (full) in projects: openbmc

Searched +full:cache +full:- +full:level (Results 1 – 25 of 1094) sorted by relevance

/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up… 10 "Unit": "CPU-M-CF", 14 …nslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a r… 17 "Unit": "CPU-M-CF", 21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress… 24 "Unit": "CPU-M-CF", 28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa… 31 "Unit": "CPU-M-CF", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	cache.json	111 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche… 114 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche… 117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi… 120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi… 123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher… 126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher… 141 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st… 144 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st… 147 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st… 150 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a … [all …]
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up… 10 "Unit": "CPU-M-CF", 14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace… 17 "Unit": "CPU-M-CF", 21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher… 108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher… 111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi… 114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi… 117 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch… 120 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch… 123 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st… 126 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st… 129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each … 132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 17 "Unit": "CPU-M-CF", 21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro… 24 "Unit": "CPU-M-CF", 28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced … 31 "Unit": "CPU-M-CF", 35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced … [all …]
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up… 10 "Unit": "CPU-M-CF", 14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace… 17 "Unit": "CPU-M-CF", 21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc… 10 "Unit": "CPU-M-CF", 14 …"A directory write to the Level-1 Instruction Cache directory where the returned cache line was so… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 31 "Unit": "CPU-M-CF", 35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache." [all …]
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …directory write to the Level-1 Instruction Cache directory where the returned cache line was sourc… 10 "Unit": "CPU-M-CF", 14 …"A directory write to the Level-1 Data Cache directory where the installed cache line was sourced … 17 "Unit": "CPU-M-CF", 21 …Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 ca… 24 "Unit": "CPU-M-CF", 28 …Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that… 31 "Unit": "CPU-M-CF", 35 …Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cach… [all …]
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	l2_cache.json	4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access… 8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru… 12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP… 20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an… 24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a… 28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access… 32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access… 36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t… 40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio… 44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,… [all …]
H A D	l1d_cache.json	4 …level 1 data cache refills caused by speculatively executed load or store operations that missed i… 8 …level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the … 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o… 20 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper… 24 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts … 28 …level 1 data cache refills caused by speculatively executed load instructions where the memory rea… 32 …level 1 data cache refills caused by speculatively executed store instructions where the memory wr… 36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… [all …]
H A D	metrics.json	4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC… 15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) \| strcmp… 61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - … 101 …level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives … 103 "ScaleUnit": "1per cache access" 108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 115 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give… 122 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 129 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse… 131 "ScaleUnit": "1per cache access" [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access… 8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru… 12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP… 20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an… 24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a… 28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access… 32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access… 36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t… 40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio… 44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
H A D	l1d_cache.json	4 …level 1 data cache refills caused by speculatively executed load or store operations that missed i… 8 …level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the … 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 16 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper… 20 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts … 24 …level 1 data cache refills caused by speculatively executed load instructions where the memory rea… 28 …level 1 data cache refills caused by speculatively executed store instructions where the memory wr… 32 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 36 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… 40 … dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. Thi… [all …]
/openbmc/linux/arch/powerpc/kernel/
H A D	cacheinfo.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Processor cache information made available to userspace via sysfs; 26 /* per-cpu object for tracking: 27 * - a "cache" kobject for the top-level directory 28 * - a list of "index" objects representing the cpu's local cache hierarchy 31 struct kobject kobj; / bare (not embedded) kobject for cache 36 /* "index" object: each cpu's cache directory has an index 37 * subdirectory corresponding to a cache object associated with the 43 struct cache cache; member 47 cache type */ [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A D	recommended.json	3 "PublicDescription": "Attributable Level 1 data cache access, read", 6 "BriefDescription": "L1D cache access, read" 9 "PublicDescription": "Attributable Level 1 data cache access, write", 12 "BriefDescription": "L1D cache access, write" 15 "PublicDescription": "Attributable Level 1 data cache refill, read", 18 "BriefDescription": "L1D cache refill, read" 21 "PublicDescription": "Attributable Level 1 data cache refill, write", 24 "BriefDescription": "L1D cache refill, write" 27 "PublicDescription": "Attributable Level 1 data cache refill, inner", 30 "BriefDescription": "L1D cache refill, inner" [all …]
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A D	cpufreq-qcom-hw.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 21 - description: v1 of CPUFREQ HW 23 - enum: 24 - qcom,qcm2290-cpufreq-hw 25 - qcom,sc7180-cpufreq-hw 26 - qcom,sdm845-cpufreq-hw [all …]`
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache [all …]
/openbmc/linux/arch/arm64/boot/dts/apple/
H A D	t600x-common.dtsi	`1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 11 #address-cells = <2>; 12 #size-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <0>; 18 cpu-map { 63 enable-method = "spin-table"; 64 cpu-release-addr = <0 0>; /* To be filled by loader */ 65 next-level-cache = <&l2_cache_0>; 66 i-cache-size = <0x20000>; [all …]`
/openbmc/qemu/qapi/
H A D	machine-common.json	1 # -- Mode: Python -- 5 # See the COPYING file in the top-level directory. 27 # @thread: thread level, which would also be called SMT level or 28 # logical processor level. The @threads option in 30 # level. 32 # @core: core level. The @cores option in SMPConfiguration is used 33 # to configure the topology of this level. 35 # @module: module level. The @modules option in SMPConfiguration is 36 # used to configure the topology of this level. 38 # @cluster: cluster level. The @clusters option in SMPConfiguration [all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A D	sm4450.dtsi	`1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 interrupt-parent = <&intc>; 12 #address-cells = <2>; 13 #size-cells = <2>; 18 xo_board: xo-board { 19 compatible = "fixed-clock"; 20 clock-frequency = <76800000>; 21 #clock-cells = <0>; [all …]`

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